TS80C51RA2 Atmel Corporation, TS80C51RA2 Datasheet - Page 43

• Manufacturer Part Number: TS80C51RA2
• Description: High Performance 8-bit Microcontroller
• Manufacturer: Atmel Corporation

Idle Mode
Power-down Mode
Figure 17. Power-Down Exit Waveform
4188A–8051–10/02
XTAL1
INT0
INT1
Active phase
An instruction that sets PCON.0 causes that to be the last instruction executed before
going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the
CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is pre-
served in its entirety: the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold
the logical states they had at the time Idle was activated. ALE and PSEN hold at logic
high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be ser-
viced, and following RETI the next instruction to be executed will be the one following
the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured dur-
ing normal operation or during an Idle. For example, an instruction that activates Idle
can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt
service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock
oscillator is still running, the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the reset.
To save maximum power, a power-down mode can be invoked by software (Refer to
Table 19, PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-
down mode is the last instruction executed. The internal RAM and SFRs retain their
value until the power-down mode is terminated. V
power. Either a hardware reset or an external interrupt can cause an exit from power-
down. To properly terminate power-down, the reset or external interrupt should not be
executed before V
long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that,
interrupt must be enabled and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as
detailed in Figure 17. When both interrupts are enabled, the oscillator restarts as soon
as one of the two inputs is held low and power down exit will be completed when the first
input will be released. In this case the higher priority interrupt service routine is exe-
cuted.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the
one following the instruction that put TS80C51Rx2 into power-down mode.
Power-down phase
CC
is restored to its normal operating level and must be held active
Oscillator restart phase
CC
Active phase
can be lowered to save further
TS8xC51Rx2
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