74HCT273D,653 NXP Semiconductors, 74HCT273D,653 Datasheet - Page 15

• Manufacturer Part Number: 74HCT273D,653
• Description: IC FLIP FLOP OCT D RESET 20SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr
• Type: D-Type Busr

Specifications of 74HCT273D,653

• Package / Case: 20-SOIC (7.5mm Width)
• Function: Master Reset
• Output Type: Non-Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 36MHz
• Delay Time - Propagation: 15ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 4mA, 4mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: HCT
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 15 ns
• High Level Output Current: - 4 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1534-2; 74HCT273D-T; 933715550653

Philips Semiconductors
Table 10:
Voltages are referenced to GND (ground = 0 V); t
Figure
[1]
74HC_HCT273_3
Product data sheet
Symbol Parameter
t
t
t
f
C
T
t
t
t
t
t
t
t
t
t
f
T
t
t
t
t
t
t
t
t
t
f
rec
su
h
max
PHL
PLH
PHL
THL
TLH
W
rec
su
h
max
PHL
PLH
PHL
THL
TLH
W
rec
su
h
max
amb
amb
PD
,
,
,
,
C
P
f
f
C
V
N = number of inputs switching;
i
o
D
CC
= 40 C to +85 C
= 40 C to +125 C
PD
= input frequency in MHz;
L
= output frequency in MHz;
10.
= output load capacitance in pF;
= C
is used to determine the dynamic power dissipation (P
= supply voltage in V;
recovery time MR to CP
set-up time Dn to CP
hold time Dn to CP
maximum input clock frequency
power dissipation capacitance
propagation delay CP to Qn
HIGH-to-LOW propagation delay
MR to Qn
output transition time
pulse width
recovery time MR to CP
set-up time Dn to CP
hold time Dn to CP
maximum input clock frequency
propagation delay CP to Qn
HIGH-to-LOW propagation delay
MR to Qn
output transition time
pulse width
recovery time MR to CP
set-up time Dn to CP
hold time Dn to CP
maximum input clock frequency
PD
Dynamic characteristics 74HCT273
clock HIGH or LOW
master reset LOW
clock HIGH or LOW
master reset LOW
V
CC
2
f
i
N + (C
L
V
CC
2
f
o
) where:
Conditions
V
V
V
see
per flip-flop; V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
V
r
CC
CC
Rev. 03 — 24 January 2006
Figure 7
…continued
= t
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V; see
= 4.5 V
= 5.0 V; C
f
= 6 ns; C
D
in W).
I
Octal D-type flip-flop with reset; positive-edge trigger
= GND to (V
L
Figure 8
Figure 9
Figure 9
Figure 7
Figure 8
Figure 7
Figure 7
Figure 8
Figure 8
Figure 9
Figure 9
Figure 7
Figure 7
Figure 8
Figure 7
Figure 7
Figure 8
Figure 8
Figure 9
Figure 9
Figure 7
L
= 15 pF
= 50 pF unless otherwise specified; for test circuit see
CC
74HC273; 74HCT273
1.5 V)
[1]
Min
+10
12
+3
30
-
-
-
-
-
20
20
13
15
3
24
-
-
-
24
24
15
18
3
20
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Typ
5
56
36
23
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
4
Max
-
-
-
-
-
-
38
43
19
-
-
-
-
-
-
45
51
22
-
-
-
-
-
-
Unit
ns
ns
ns
MHz
MHz
pF
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
MHz
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