MCS9845 MosChip Semiconductor, MCS9845 Datasheet - Page 21

• Manufacturer Part Number: MCS9845
• Description: PCI Dual UART
• Manufacturer: MosChip Semiconductor

Rev. 2.5
Scratch Pad Register (SPR)
The scratch pad register is an 8-bit register that can
be used by the programmer to store any data without
affecting any other registers or device operation. The
contents of this register are volatile, the data will be lost
when the device is reset, or when power is removed.
Programmable Baud-Rate Generator
A programmable Baud Rate Generator is provided
that typically takes a clock input of 1.8432 MHz and
divides it by a divisor in the range between 1 and (2
1). The output frequency of the Baud Rate Generator
is 16 times the desired Baud Rate. Two 8-bit registers,
called Divisor Latches, store the divisor in a 16-bit
binary format. These Divisor Latches must be loaded
during the device’s initialization in order to ensure
correct operation of the Baud Rate Generator. When
either of the Divisor Latches is altered, an internal
16-bit Baud Counter is also updated to prevent long
counts on the initial load.
Baud Rate Generator programming table for the
default 1.8432 MHz clock (12XCLK).
MosChip devices with Serial Ports provide the 12XCLK
output signal that can be used as the input clock for
the UART. 12XCLK is the standard 1.8432 MHz clock.
Using this signal as the clock input will generate the
expected Baud Rates as shown in the table above.
Baud Out
115.2K
57.6K
38.4K
19.2K
9600
4800
2400
1200
600
300
150
50
(hex)
DLM
00
00
00
00
00
00
00
00
00
01
03
09
(hex)
DLL
0C
C0
01
02
03
06
18
30
60
80
00
00
16
-
FIFO Interrupt Mode Operation
When the receiver FIFO and receiver interrupts are
enabled (FCR-0=1, IER-0=1, IER-2=1), a receiver
interrupt occurs as follows:
The Received Data Available interrupt is issued when
the FIFO has reached its programmed trigger level. It
is cleared when the FIFO drops below its programmed
trigger level. The IIR Receive Data Available indication
also occurs when the FIFO trigger level is reached,
and like the interrupt, it is cleared when the FIFO drops
below the trigger level.
The receiver Line Status Interrupt has higher priority
than the Received Data Available interrupt. The data
ready bit (LSR-0) is set when a character is transferred
from the shift register to the receiver FIFO. It is reset
when the FIFO is empty.
When the receiver FIFO and receiver interrupts are
enabled, the FIFO Time-Out interrupt occurs when the
following conditions exist:
When a Time-Out interrupt has occurred, it is cleared
and the timer is reset when the microprocessor reads
one character from the receiver FIFO. Even if a Time-
Out interrupt has not occurred, the time-out timer is
reset each time a new character is received or when
the microprocessor reads the receiver FIFO.
Character Time-Out and receiver FIFO Trigger-
Level interrupts have the same priority as the current
Receiver Data Available interrupt.
•
•
•
At least one character is in the FIFO.
The most recent serial character was
received more than four continuous character
times ago (if two stop bits are programmed,
the second one is included in this time
delay).
The most recent microprocessor read of the
FIFO occurred more than fi ve continuous
character times ago.
PCI Dual UART with ISA Bridge
MCS9845
www.DataSheet4U.com
Page 21