MCS9845 MosChip Semiconductor, MCS9845 Datasheet - Page 8

• Manufacturer Part Number: MCS9845
• Description: PCI Dual UART
• Manufacturer: MosChip Semiconductor

Page 8
MCS9845
PCI Dual UART with ISA Bridge
PCI Bus Operation:
The execution of PCI Bus transactions take place
in broadly fi ve stages: address phase; transaction
claiming; data phase(s); fi nal data transfer; and
transaction completion.
Address Phase:
Every PCI transaction starts with an address phase,
one PCI clock period in duration. During the address
phase the initiator (also known as the current Bus
Master) identifi es the target device (via the address)
and type of transaction (via the command). The initiator
drives the 32-bit address onto the Address/Data Bus,
and a 4-bit command onto the Command/Byte-Enable
Bus. The initiator also asserts the nFRAME signal
during the same clock cycle to indicate the presence
of valid address and transaction information on those
buses. The initiator supplies the starting address and
command type for one PCI clock cycle. The target
generates the subsequent sequential addresses
for burst transfers. The Address/Data Bus becomes
the Data Bus, and the Command/Byte-Enable Bus
becomes the Byte-Enable Bus for the remainder of the
clock cycles in that transaction. The target latches the
address and command type on the next rising edge
of PCI clock, as do all other devices on that PCI bus.
Each device then decodes the address and determines
whether it is the intended target, and also decodes the
command to determine the type of transaction.
Claiming The Transaction:
When a device determines that it is the target of a
transaction, it claims the transaction by asserting
nDEVSEL.
Data Phase(s):
The data phase of a transaction is the period during
which a data object is transferred between the
initiator and the target. The number of data Bytes to
be transferred during a data phase is determined by
the number of Command/Byte-Enable signals that
are asserted by the initiator during the data phase.
Each data phase is at least one PCI clock period in
duration. Both initiator and target must indicate that
they are ready to complete a data phase. If not, the
data phase is extended by a wait state of one clock
period in duration. The initiator and the target indicate
this by asserting nIRDY and nTRDY respectively and
the data transfer is completed at the rising edge of the
next PCI clock.
Transaction Duration:
The initiator, as stated earlier, gives only the starting
address during the address phase. It does not tell the
number of data transfers in a burst transfer transaction.
The target will automatically generate the addresses
for subsequent Data Phase transfers. The initiator
indicates the completion of a transaction by asserting
nIRDY and de-asserting nFRAME during the last data
transfer phase. The transaction does not actually
complete until the target has also asserted the nTRDY
signal and the last data transfer takes place. At this
point the nTRDY and nDEVSEL are de-asserted by
the target.
Transaction Completion:
When all of nIRDY, nTRDY, nDEVSEL, and nFRAME
are in the inactive state (high state), the bus is in idle
state. The bus is then ready to be claimed by another
Bus Master.
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