LT1355 Linear Technology, LT1355 Datasheet - Page 10

• Manufacturer Part Number: LT1355
• Description: Dual and Quad 12MHz/ 400V/us Op Amps
• Manufacturer: Linear Technology

APPLICATIONS
LT1355/LT1356
Capacitive Loading
The LT1355/LT1356 are stable with any capacitive load.
As the capacitive load increases, both the bandwidth and
phase margin decrease so there will be peaking in the
frequency domain and in the transient response. Coaxial
cable can be driven directly, but for best pulse fidelity a
resistor of value equal to the characteristic impedance of
the cable (i.e., 75 ) should be placed in series with the
output. The other end of the cable should be terminated
with the same value resistor to ground.
Input Considerations
Each of the LT1355/LT1356 inputs is the base of an NPN
and a PNP transistor whose base currents are of opposite
polarity and provide first-order bias current cancellation.
Because of variation in the matching of NPN and PNP beta,
the polarity of the input bias current can be positive or
negative. The offset current does not depend on NPN/PNP
beta matching and is well controlled. The use of balanced
source resistance at each input is recommended for
applications where DC accuracy must be maximized.
The inputs can withstand transient differential input volt-
ages up to 10V without damage and need no clamping or
source resistance for protection. Differential inputs, how-
ever, generate large supply currents (tens of mA) as
required for high slew rates. If the device is used with
sustained differential inputs, the average supply current
will increase, excessive power dissipation will result and
the part may be damaged. The part should not be used as
a comparator, peak detector or other open-loop applica-
tion with large, sustained differential inputs. Under
normal, closed-loop operation, an increase of power dis-
sipation is only noticeable in applications with large slewing
outputs and is proportional to the magnitude of the
differential input voltage and the percent of the time that
the inputs are apart. Measure the average supply current
for the application in order to calculate the power dissipa-
tion.
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INFORMATION
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Circuit Operation
The LT1355/LT1356 circuit topology is a true voltage
feedback amplifier that has the slewing behavior of a
current feedback amplifier. The operation of the circuit can
be understood by referring to the simplified schematic.
The inputs are buffered by complementary NPN and
PNP emitter followers which drive an 800 resistor. The
input voltage appears across the resistor generating
currents which are mirrored into the high impedance
node. Complementary followers form an output stage
which buffers the gain node from the load. The bandwidth
is set by the input resistor and the capacitance on the high
impedance node. The slew rate is determined by the
current available to charge the gain node capacitance.
This current is the differential input voltage divided by R1,
so the slew rate is proportional to the input. Highest slew
rates are therefore seen in the lowest gain configurations.
For example, a 10V output step in a gain of 10 has only a
1V input step, whereas the same output step in unity gain
has a 10 times greater input step. The curve of Slew Rate
vs Input Level illustrates this relationship. The LT1355/
LT1356 are tested for slew rate in a gain of –2 so higher
slew rates can be expected in gains of 1 and –1, and lower
slew rates in higher gain configurations.
The RC network across the output stage is bootstrapped
when the amplifier is driving a light or moderate load and
has no effect under normal operation. When driving a
capacitive load (or a low value resistive load) the network
is incompletely bootstrapped and adds to the compensa-
tion at the high impedance node. The added capacitance
slows down the amplifier which improves the phase
margin by moving the unity-gain frequency away from the
pole formed by the output impedance and the capacitive
load. The zero created by the RC combination adds phase
to ensure that even for very large load capacitances, the
total phase lag can never exceed 180 degrees (zero phase
margin) and the amplifier remains stable.