LT1719 Linear Technology, LT1719 Datasheet - Page 10

• Manufacturer Part Number: LT1719
• Description: 4ns/ 150MHz Dual Comparator with Independent Input/Output Supplies
• Manufacturer: Linear Technology

APPLICATIONS
LT1719
This method will work for additional hysteresis of up to a
few hundred millivolts. Beyond that, the impedance of R3
is low enough to effect the bias string, and adjustment of
R1 may also be required. Note that the currents through the
R1/R2 bias string should be many times the input currents
of the LT1719. For 5% accuracy, the current must be at least
20 times the input current, more for higher accuracy.
Interfacing the LT1719 to ECL
The LT1719 comparators can be used in high speed
applications where Emitter-Coupled Logic (ECL) is de-
ployed. To interface the output of the LT1719 to ECL logic
inputs, standard TTL/CMOS to ECL level translators such
as the 10H124, 10H424 and 100124 can be used. These
components come at a cost of a few nanoseconds addi-
tional delay as well as supply currents of 50mA or more,
and are only available in quads. A faster, simpler and lower
power translator can be constructed with resistors as
shown in Figure 6.
Figure 6a shows the standard TTL to Positive ECL (PECL)
resistive level translator. This translator cannot be used for
the LT1719, or with CMOS logic, because it depends on the
820 resistor to limit the output swing (V
TTL gate with its so-called totem-pole output. The LT1719
is fabricated in a complementary bipolar process and the
output stage has a PNP driver that pulls the output nearly
all the way to the supply rail, even when sourcing 10mA.
Figure 6b shows a three resistor level translator for inter-
facing the LT1719 to ECL running off the same supply rail.
No pull-down on the output of the LT1719 is needed, but
pull-down R3 limits the V
needed because ECL inputs have both a minimum and
maximum V
10
Figure 5. Model for Additional Hysteresis Calculations
V
IH
REF
R2
R1
specification for proper operation. Resistor
V
TH
U
+
–
LT1719
INFORMATION
IH
U
R3
seen by the PECL gate. This is
V
AVERAGE
W
OH
1719 F05
=
+V
) of the all-NPN
2
S
U
values are given for both ECL interface types; in both cases
it is assumed that the LT1719 operates from the same
supply rail.
Figure 6c shows the case of translating to PECL from an
LT1719 powered by a 3V supply rail. Again, resistor values
are given for both ECL interface types. This time four re-
sistors are needed, although with 10KH/E, R3 is not needed.
In that case, the circuit resembles the standard TTL trans-
lator of Figure 6a, but the function of the new resistor, R4,
is much different. R4 loads the LT1719 output when high
so that the current flowing through R1 doesn’t forward
bias the LT1719’s internal ESD clamp diode. Although this
diode can handle 20mA without damage, normal opera-
tion and performance of the output stage can be impaired
above 100 A of forward current. R4 prevents this with the
minimum additional power dissipation.
Finally, Figure 6d shows the case of driving standard,
negative-rail, ECL with the LT1719. Resistor values are
given for both ECL interface types and for both a 5V and 3V
LT1719 supply rail. Again, a fourth resistor, R4 is needed
to prevent the low state current from flowing out of the
LT1719, turning on the internal ESD/substrate diodes.
Resistor R4 again prevents this with the minimum addi-
tional power dissipation.
Of course, if the V
negative supply, the GND pin can be tied to it as well and
+ V
rails as the ECL and the circuits of Figure 6b can be used.
For all the dividers shown, the output impedance is about
110 . This makes these fast, less than a nanosecond, with
most layouts. Avoid the temptation to use speedup capaci-
tors. Not only can they foul up the operation of the ECL gate
because of overshoots, they can damage the ECL inputs,
particularly during power-up of separate supply configu-
rations.
The level translator designs assume one gate load. Mul-
tiple gates can have significant I
mission line routing and termination issues also make this
case difficult.
ECL, and particularly PECL, is valuable technology for high
speed system design, but it must be used with care. With
less than a volt of swing, the noise margins need to be
S
grounded. Then the output stage has the same power
EE
of the LT1719 is the same as the ECL
IH
loading, and the trans-