LT1977 Linear Technology, LT1977 Datasheet - Page 6

• Manufacturer Part Number: LT1977
• Description: Step-Down Switching Regulator
• Manufacturer: Linear Technology

LT1977
TYPICAL PERFOR A CE CHARACTERISTICS
PI FU CTIO S
NC (Pins 1, 3, 5): No Connection.
SW (Pin 2): The SW pin is the emitter of the on-chip power
NPN switch. This pin is driven up to the input pin voltage
during switch on time. Inductor current drives the SW pin
negative during switch off time. Negative voltage is clamped
with the external catch diode. Maximum negative switch
voltage allowed is –0.8V.
V
switch. V
voltage on the BIAS pin is not present. High di/dt edges
occur on this pin during switch turn on and off. Keep the
path short from the V
capacitor, through the catch diode back to SW. All trace
inductance on this path will create a voltage spike at switch
off, adding to the V
6
IN
U
(Pin 4): This is the collector of the on-chip power NPN
IN
U
500mA/DIV
500mA/DIV
50mV/DIV
20mV/DIV
powers the internal control circuitry when a
V
V
I
OUT
OUT
OUT
I
SW
V
V
C
I
Burst Mode Operation
V
V
I
No Load 1A Step Response
DC
Q
CE
IN
OUT
OUT
IN
OUT
U
= 100µA
= 0mA
= 12V
= 12V
voltage across the internal NPN.
= 3.3V
= 100µF
= 3.3V
IN
pin through the input bypass
W
500µs/DIV
5ms/DIV
U
1977 G17
1977 G14
500mA/DIV
500mA/DIV
BOOST (Pin 6): The BOOST pin is used to provide a drive
voltage, higher than the input voltage, to the internal
bipolar NPN power switch. Without this added voltage, the
typical switch voltage loss would be about 1.5V. The
additional BOOST voltage allows the switch to saturate
and its voltage loss approximates that of a 0.2Ω FET
structure.
C
of delay time between the PGFB pin exceeding its thresh-
old (V
When the PGFB pin rises above V
from the C
age on the external capacitor reaches an internal clamp
(V
resultant PG delay time is given by t = C
50mV/DIV
20mV/DIV
T
CT
(Pin 7): A capacitor on the C
V
V
I
), the PG pin becomes a high impedance node. The
OUT
OUT
OUT
I
SW
PGFB
V
V
C
I
Burst Mode Operation
V
V
I
DC
Q
IN
OUT
OUT
IN
OUT
Step Response
= 100µA
= 12V
= 350mA
T
= 12V
) and the PG pin set to a high impedance state.
= 3.3V
= 100µF
= 3.3V
pin into the external capacitor. When the volt-
500µs/DIV
2µs/DIV
T
pin determines the amount
PGFB
1977 G18
1977 G15
, current is sourced
CT
• V
CT
/I
CT
. If the
1977f