LTC1478 Linear Technology, LTC1478 Datasheet - Page 4

• Manufacturer Part Number: LTC1478
• Description: Single and Dual Protected High Side Switches
• Manufacturer: Linear Technology

PIN
LTC1477/LTC1478
4
LTC1477
EN (Pin 4): The enable input is a high impedance CMOS
gate with an ESD protection diode to ground and should
not be forced below ground. This input has about 100mV
of built-in hysteresis to ensure clean switching.
V
connected to the V
V
the current limit and thermal shutdown circuitry; plus
provides a sense connection to the input power supply.
The gate of the NMOS switch is powered by a charge pump
from the V
supply pin provides connection to the drain of 1/2 of the
output power device.
V
typically tied to the V
resistance; i.e., when all four V
together the entire power device is connected (see Block
Diagram). Each auxiliary supply pin, V
connected to the drain of 1/4 of the power device. The V
and V
the short-circuit current limit at the expense of higher
R
details.)
V
always be tied together. The output is protected against
accidental short circuits to ground by a current limit circuit
which protects the system power supply and load against
damage. A second level of protection is provided by
thermal shutdown circuitry which limits the die tempera-
ture to 130 C.
INS
INS
IN2
OUT
DS(ON)
U
, V
, V
supply pin provides power for the input control logic,
(Pins 1,8): The output pins of the LTC1477 must
IN3
FUNCTIONS
IN1
IN3
. (See Applications Information section for more
pins can be selectively disconnected to reduce
(Pins 3,2): The V
U
(Pins 7,6): The V
INS
supply pin (see Block Diagram). The V
IN1
INS
U
supply pin (see Block Diagram). The
and V
INS
IN2
IN1
supply pin must always be
and V
supply pins for lowest ON
IN
pins are connected
IN3
IN2
supply pins are
and V
IN3
, is
IN1
IN2
LTC1478
AEN, BEN (Pins 4,12): The enable inputs are high imped-
ance CMOS gates with ESD protection diodes to ground
and should not be forced below ground. These inputs
have about 100mV of built-in hysteresis to ensure clean
switching.
AV
or BV
AV
and BV
logic, the current limit and thermal shutdown circuitry;
plus, provides a sense connection to the input power
supply. The gate of the NMOS switch is powered by a
charge pump from the AV
Block Diagram). The AV
connection to the drain of 1/2 of the output power device.
AV
AV
AV
resistance; i.e., when all four AV
nected together the entire power device is connected (see
Block Diagram). Each auxiliary supply pin, AV
BV
mately 1/4 of the corresponding power device. The AV
AV
nected to reduce the short-circuit current limit at the
expense of higher R
section for more details.)
AV
are protected against accidental short circuits to ground
by a current limit circuit which protects the system power
supplies and loads against damage. A second level of
protection is provided by thermal shutdown circuitry
which limits the die temperature to approximately 130 C.
OUT
INS
IN1
IN2
IN3
INS
IN2
IN3
, AV
, BV
, BV
, AV
, AV
INS
or BV
, BV
and BV
INS
IN2
supply pin must always be connected to the
IN3
IN1
IN1
IN2
OUT
supply pins provide power for the input control
IN1
, BV
, BV
, BV
and BV
and BV
IN3
(Pins 1,16; 8,9): The outputs of the LTC1478
supply pin (see Block Diagram). The AV
IN2
INS
, is connected to the drain of approxi-
INS
DS(ON)
, BV
IN3
, BV
and BV
IN3
supply pins are typically tied to the
IN1
IN3
IN1
pins can be selectively discon-
INS
. (See Applications Information
, (Pins 15,14; 7,6): The AV
and BV
(Pins 3,2; 11,10): The AV
IN1
and BV
supply pins for lowest ON
IN1
IN
, BV
INS
supply pins provide
supply pins (see
IN
pins are con-
IN2
, AV
IN2
IN3
IN2
INS
INS
,
,
,