LTC1735I-1 Linear Technology, LTC1735I-1 Datasheet - Page 12

• Manufacturer Part Number: LTC1735I-1
• Description: High Efficiency Synchronous Step-Down Switching Regulator
• Manufacturer: Linear Technology

LTC1735-1
APPLICATIO S I FOR ATIO
Inductor Core Selection
Once the value for L is known, the type of inductor must be
selected. High efficiency converters generally cannot afford
the core loss found in low cost powdered iron cores,
forcing the use of more expensive ferrite, molypermalloy,
or Kool M
size for a fixed inductor value, but it is very dependent on
inductance selected. As inductance increases, core losses
go down. Unfortunately, increased inductance requires
more turns of wire and therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
loss core material for toroids, but it is more expensive than
ferrite. A reasonable compromise from the same
manufacturer is Kool M . Toroids are very space efficient,
especially when you can use several layers of wire. Because
they generally lack a bobbin, mounting is more difficult.
However, designs for surface mount are available that do
not increase the height significantly.
Power MOSFET and D1 Selection
Two external power MOSFETs must be selected for use
with the LTC1735-1: an N-channel MOSFET for the top
(main) switch, and an N-channel MOSFET for the bottom
(synchronous) switch.
The peak-to-peak gate drive levels are set by the INTV
voltage. This voltage is typically 5.2V during start-up (see
EXTV
threshold MOSFETs must be used in most LTC1735-1
applications. The only exception is when low input voltage
is expected (V
MOSFETs (V
attention to the BV
well; most of the logic level MOSFETs are limited to 30V or
less.
Kool M is a registered trademark of Magnetics, Inc.
12
CC
Pin Connection). Consequently, logic-level
®
cores. Actual core loss is independent of core
GS(TH)
IN
< 5V); then, sub-logic level threshold
DSS
U
< 3V) should be used. Pay close
specification for the MOSFETs as
U
W
U
CC
Selection criteria for the power MOSFETs include the “ON”
resistance R
input voltage and maximum output current. When the
LTC1735-1 is operating in continuous mode the duty
cycles for the top and bottom MOSFETs are given by:
The MOSFET power dissipations at maximum output
current are given by:
where is the temperature dependency of R
is a constant inversely related to the gate drive current.
Both MOSFETs have I
N-channel equation includes an additional term for transi-
tion losses, which are highest at high input voltages. For
V
with larger MOSFETs, while for V
losses rapidly increase to the point that the use of a higher
R
efficiency. The synchronous MOSFET losses are greatest
at high input voltage or during a short circuit when the duty
cycle in this switch is nearly 100%.
The term (1 + ) is generally given for a MOSFET in the
form of a normalized R
voltage MOSFETs. C
MOSFET characteristics. The constant k = 1.7 can be used
to estimate the contributions of the two terms in the main
switch dissipation equation.
The Schottky diode D1 shown in Figure 1 conducts during
the dead-time between the conduction of the two power
MOSFETs. This prevents the body diode of the bottom
IN
DS(ON)
= 0.005/ C can be used as an approximation for low
Main Switch Duty Cycle
P
Synchronous Switch Duty Cycle
P
< 20V the high current efficiency generally improves
SYNC
MAIN
device with lower C
k V
V
V
DS(ON)
V
IN
OUT
IN
IN
–
V
IN
V
2
I
, reverse transfer capacitance C
OUT
MAX
I
MAX
RSS
DS(ON)
2
I
MAX
2
R losses while the topside
1
C
is usually specified in the
RSS
RSS
2
vs Temperature curve, but
V
V
OUT
1
IN
R
actually provides higher
DS ON
IN
f
(
> 20V the transition
R
V
)
DS ON
IN
(
–
V
IN
DS(ON)
V
)
OUT
and k
RSS
,