LTC2247 Linear Technology, LTC2247 Datasheet - Page 19

• Manufacturer Part Number: LTC2247
• Description: (LTC2246 - LTC2248) 65/40/25Msps Low Power 3V ADCs
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
As with all high speed/high resolution converters, the
digital output loading can affect the performance. The
digital outputs of the LTC2248/LTC2247/LTC2246 should
drive a minimal capacitive load to avoid possible interac-
tion between the digital outputs and sensitive input cir-
cuitry. The output should be buffered with a device such as
an ALVCH16373 CMOS latch. For full speed operation the
capacitive load should be kept under 10pF.
Lower OV
from the digital outputs.
Data Format
Using the MODE pin, the LTC2248/LTC2247/LTC2246
parallel digital output can be selected for offset binary or
2’s complement format. Connecting MODE to GND or
1/3V
MODE to 2/3V
format. An external resistor divider can be used to set the
1/3V
states for the MODE pin.
Table 2. MODE Pin Function
MODE Pin
0
1/3V
2/3V
V
Overflow Bit
When OF outputs a logic high the converter is either
overranged or underranged.
DD
DD
DD
DD
DD
selects offset binary output format. Connecting
or 2/3V
DD
voltages will also help reduce interference
DD
2’s Complement
2’s Complement
DD
Output Format
Offset Binary
Offset Binary
or V
logic values. Table 2 shows the logic
U
DD
selects 2’s complement output
U
W
Cycle Stablizer
Clock Duty
Off
On
On
Off
U
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OV
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 1.8V
supply, then OV
OV
3.6V. OGND can be powered with any voltage from GND up
to 1V and must be less than OV
swing between OGND and OV
Output Enable
The outputs may be disabled with the output enable pin, OE.
OE high disables all data outputs including OF. The data ac-
cess and bus relinquish times are too slow to allow the
outputs to be enabled and disabled during full speed op-
eration. The output Hi-Z state is intended for use during long
periods of inactivity.
Sleep and Nap Modes
The converter may be placed in shutdown or nap modes
to conserve power. Connecting SHDN to GND results in
normal operation. Connecting SHDN to V
results in sleep mode, which powers down all circuitry
including the reference and typically dissipates 1mW. When
exiting sleep mode it will take milliseconds for the output
data to become valid because the reference capacitors have
to recharge and stabilize. Connecting SHDN to V
to GND results in nap mode, which typically dissipates
15mW. In nap mode, the on-chip reference circuit is kept
on, so that recovery from nap mode is faster than that from
sleep mode, typically taking 100 clock cycles. In both sleep
and nap modes, all digital outputs are disabled and enter
the Hi-Z state.
LTC2248/LTC2247/LTC2246
DD
can be powered with any voltage from 500mV up to
DD
should be tied to that same 1.8V supply.
DD
DD
.
. The logic outputs will
DD
DD
, should be tied
and OE to V
DD
19
and OE
224876fa
DD