LTC2293 Linear Technology, LTC2293 Datasheet - Page 12

• Manufacturer Part Number: LTC2293
• Description: (LTC2291 - LTC2293) 65/40/25Msps Low Power 3V ADCs
• Manufacturer: Linear Technology

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PI FU CTIO S
LTC2293/LTC2292/LTC2291
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA13, OFA; Channel B
comes out on DB0-DB13, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0-
DB13, OFB; Channel B comes out on DA0-DA13, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together.
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to V
tion with the outputs at high impedance. Connecting
SHDNB to V
the outputs at high impedance. Connecting SHDNB to V
and OEB to V
high impedance.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
NC (Pins 24, 25, 41, 42): Do Not Connect These Pins.
DB0 – DB11 (Pins 26 to 30, 33 to 39): Channel B Digital
Outputs. DB11 is the MSB.
OGND (Pins 31, 50): Output Driver Ground.
OV
ers. Bypass to ground with 0.1µF ceramic chip capacitor.
OFB (Pin 40): Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
DA0 – DA11 (Pins 43 to 48, 51 to 56): Channel A Digital
Outputs. DA11 is the MSB.
OFA (Pin 57): Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.
12
U
DD
(Pins 32, 49): Positive Supply for the Output Driv-
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DD
DD
and OEB to GND results in nap mode with
results in sleep mode with the outputs at
U
DD
results in normal opera-
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DD
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to V
tion with the outputs at high impedance. Connecting
SHDNA to V
the outputs at high impedance. Connecting SHDNA to V
and OEA to V
high impedance.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects straight bi-
nary output format and turns the clock duty cycle stabilizer
off. 1/3 V
the clock duty cycle stabilizer on. 2/3 V
complement output format and turns the clock duty cycle
stabilizer on. V
and turns the clock duty cycle stabilizer off.
V
Mode Bias. Bypass to ground with 2.2µF ceramic chip
capacitor. Do not connect to V
SENSEA (Pin 62): Channel A Reference Programming Pin.
Connecting SENSEA to V
and a ±0.5V input range. V
and a ±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of ±V
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
CMA
(Pin 61): Channel A 1.5V Output and Input Common
DD
selects straight binary output format and turns
SENSEA
DD
DD
DD
and OEA to GND results in nap mode with
results in sleep mode with the outputs at
selects 2’s complement output format
. ±1V is the largest valid input range.
CMA
DD
selects the internal reference
selects the internal reference
DD
CMB
results in normal opera-
.
DD
selects 2’s
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DD
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