LTC2492 Linear Technology, LTC2492 Datasheet - Page 17

• Manufacturer Part Number: LTC2492
• Description: 24-Bit 2-/4-Channel ADC
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
Bit 28 (fourth output bit) is the most signifi cant bit (MSB) of
the result. This bit in conjunction with Bit 29 also provides
underrange and overrange indication. If both Bit 29 and
Bit 28 are HIGH, the differential input voltage is above
+FS. If both Bit 29 and Bit 28 are LOW, the differential
input voltage is below –FS. The function of these bits is
summarized in Table 1.
Table 1. LTC2492 Status Bits
Input Range
V
0V ≤ V
–0.5 • V
V
Bits 28 to 5 are the 24-bit conversion result MSB fi rst.
Bit 5 is the least signifi cant bit (LSB
Bits 4 to 0 are sub LSBs below the 24-bit level. Bits 4 to
0 may be included in averaging or discarded without loss
of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCK) (see Figure 3). Whenever CS is HIGH,
SDO remains high impedance and SCK is ignored.
In order to shift the conversion result out of the device,
CS must fi rst be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes in real
time as a function of the internal oscillator or the clock
applied to the f
of a conversion. This signal may be used as an interrupt for
IN
IN
≥ 0.5 • V
< –0.5 • V
(EXTERNAL)
IN
REF
< 0.5 • V
SDO
SCK
SDI
CS
≤ V
REF
CONVERSION
REF
IN
DON'T CARE
< 0V
REF
O
pin from HIGH to LOW at the completion
SLEEP
Figure 3. Channel Selection, Confi guration Selection and Data Output Timing
Bit 31
EOC
0
0
0
0
BIT 31
1
EOC
1
BIT 30
“0”
0
2
Bit 30
DMY
0
0
0
0
24
BIT 29
SIG
EN
).
3
BIT 28 BIT 27 BIT 26 BIT 25 BIT 24 BIT 23 BIT 22 BIT 21 BIT 20 BIT 19
MSB
SGL
Bit 29
4
SIG
1
1
0
0
ODD
5
Bit 28
MSB
A2
6
1
0
1
0
DATA INPUT/OUTPUT
A1
7
A0
8
an external microcontroller. Bit 31 (EOC) can be captured
on the fi rst rising edge of SCK. Bit 30 is shifted out of the
device on the fi rst falling edge of SCK. The fi nal data bit
(Bit 0) is shifted out on the on the falling edge of the 31st
SCK and may be latched on the rising edge of the 32nd SCK
pulse. On the falling edge of the 32nd SCK pulse, SDO goes
HIGH indicating the initiation of a new conversion cycle.
This bit serves as EOC (Bit 31) for the next conversion
cycle. Table 2 summarizes the output data format.
As long as the voltage on the IN
between –0.3V and V
operating range) a conversion result is generated for any
differential input voltage V
+FS = 0.5 • V
than +FS, the conversion result is clamped to the value
corresponding to +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
–FS – 1LSB.
INPUT DATA FORMAT
The LTC2492 serial input word is 13 bits long and contains
two distinct sets of data. The fi rst set (SGL, ODD, A2, A1, A0)
is used to select the input channel. The second set of data
(IM, FA, FB, SPD) is used to select the frequency rejection,
speed mode (1×, 2×), and temperature measurement.
After power up, the device initiates an internal reset cycle
which sets the input channel to CH0 to CH1 (IN
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
and 1× output rate (auto-calibration enabled). The fi rst
EN2
9
IM
10
FA
11
REF
FB
. For differential input voltages greater
12
SPD
13
CC
BIT 18 BIT 17
14
IN
+ 0.3V (absolute maximum
DON'T CARE
from –FS = –0.5 • V
+
and IN
LTC2492
BIT 0
32
–
pins remains
+
= CH0, IN
17
2492 F03
REF
2492fb
–
to
=