LTC2904 Linear Technology, LTC2904 Datasheet - Page 11

• Manufacturer Part Number: LTC2904
• Description: (LTC2904 / LTC2905) Precision Dual Supply Monitors
• Manufacturer: Linear Technology

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APPLICATIO S I FOR ATIO
Figure 1 shows the desired delay time as a function of the
value of the timer capacitor that should be used:
Leaving the TMR pin open with no external capacitor
generates a reset time-out of approximately 200µs. For
long reset time-out, the only limitation is the availability of
large value capacitor with low leakage. The TMR capacitor
will never charge if the leakage current exceeds the mini-
mum TMR charging current of 2.1µA (typical).
RST and RST Output Characteristics
The DC characteristics of the RST and RST pull-up and
pull-down strength are shown in the Typical Performance
Characteristics section. Both RST and RST have a weak
internal pull-up to V
down to ground.
The weak pull-up and strong pull-down arrangement allow
these two pins to have open-drain behavior while possess-
ing several other beneficial characteristics.
The weak pull-ups eliminate the need for external pull-up
resistors when the rise time on these pins is not critical. On
the other hand, the open-drain RST configuration allows
for wired-OR connections and can be useful when more
than one signal needs to pull down on the RST line.
Figure 1. Reset Time-Out Period vs Capacitance
10000
1000
100
0.1
10
1
10p
U
CC
100p
= Max (V1, V2) and a strong pull-
U
C
TMR
1n
(FARAD)
10n
W
100n
29045 F01
1µ
U
As noted in the Power-Up and Power-Down sections the
circuits that drive RST and RST are powered by V
During fault condition, V
maximum V
weak pull-up current on RST is barely turned on. There-
fore, an external pull-up resistor of no more than 100k is
recommended on the RST pin if the state and pull-up
strength of the RST pin is crucial at very low V
Note however, by adding an external pull-up resistor, the
pull-up strength on the RST pin is increased. Therefore, if
it is connected in a wired-OR connection, the pull-down
strength of any single device needs to accommodate this
additional pull-up strength.
Output Rise and Fall Time Estimation
The RST and RST outputs have strong pull-down capabil-
ity. The following formula estimates the output fall time
(90% to 10%) for a particular external load capacitance
(C
where R
transistor estimated to be typically 40Ω at room tempera-
ture (25°C) and C
the pin. Assuming a 150pF load capacitance, the fall time
is about 13ns.
The rise time, on the RST and RST pins is limited by weak
internal pull-up current sources to V
formula estimates the output rise time (10% to 90%) at the
RST and RST pins:
where R
Notice that this pull-up transistor is modeled as a 6µA
current source in the Block Diagram as a typical represen-
tation.
The on-resistance as a function of the V
voltage (for V
LOAD
t
t
FALL
RISE
):
≈ 2.2 • R
≈ 2.2 R
PD
PU
is the on-resistance of the internal pull-down
is the on-resistance of the pull-up transistor.
OL
CC
= 0.4V at RST. However, at V
> 1V) at room temperature is estimated as
PU
PD
LOAD
• C
• C
LTC2904/LTC2905
LOAD
is the external load capacitance on
LOAD
CC
of at least 1V guarantees a
CC
CC
. The following
= Max (V1, V2)
CC
sn29045 29045fs
CC
= 1V the
.
11
CC
.