LTC3417 Linear Technology, LTC3417 Datasheet - Page 18

• Manufacturer Part Number: LTC3417
• Description: Dual Synchronous 1.4A/800mA 4MHz Step-Down DC/DC Regulator
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC3417
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3417. These items are also illustrated graphically in
the layout diagram of Figure 5. Check the following in your
layout.
1. Does the capacitor C
2. Are the C
3. The resistor divider, R1 and R2, must be connected
18
(Pin 2), V
close as possible (DFN package)? It may be necessary
to split C
the AC current to the internal power MOSFETs and
their drivers.
(–) plate of C
(–) plate of C
and the (–) plate of C
between the (+) plate of C
terminated near GNDA. The resistor divider, R3 and R4,
IN
OUT1
IN2
into two capacitors. This capacitor provides
OUT2
, L
OUT1
(Pin 8), and PGND2/GNDD (Pin 17) as
1
U
and C
returns current to the PGND2/GNDD
returns current to PGND1, and the
STAR TO
IN
GNDA
IN
OUT2
C
V
.
U
OUT2
OUT2
V
V
connect to the power V
IN
IN
, L
10µF
OUT1
C
2
IN
closely connected? The
C
ITH2
W
and a ground line
C
0.1µF
C2
C
R
IN2
R3
R4
R8
L2
ITH2
U
V
PGND2/
EXPOSED PAD
GNDA
SW2
V
I
PGOOD
RUN2
PHASE
TH2
IN2
FB2
IN1
LTC3417
Figure 5
GNDD
4. Keep sensitive components away from the SW pins.
5. A ground plane is preferred, but if not available, keep the
6. Flood all unused areas on all layers with copper. Flood-
PGND1
MODE
RUN1
FREQ
must be connected between the (+) plate of C
a ground line terminated near GNDA. The feedback
signals V
components and traces, such as the SW lines, and its
trace should be minimized.
The input capacitor C
C
R4, R
traces and the inductors L1 and L2.
signal and power grounds segregated with small signal
components returning to the GNDA pin at one point
which is then connected to the PGND2/GNDD pin.
ing with copper will reduce the temperature rise of
power components. These copper areas should be
connected to one of the input supplies.
SW1
V
V
I
TH1
FB1
IN1
C1
, C
ITH1
C2
, C
FB1
R
and R
ITH1
L1
R1
R2
R7
C
0.1µF
ITH1
IN1
and V
C
C1
ITH2
C
and C
ITH1
FB2
should be routed away from the SW
should be routed away from noise
ITH2
IN
, the compensation capacitors
C
V
V
OUT1
OUT1
IN
STAR TO
and all resistors R1, R2, R3,
GNDA
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OUT2
3417fb
and