LTC3555 Linear Technology, LTC3555 Datasheet - Page 29

no-image

LTC3555

Manufacturer Part Number
LTC3555
Description
High Efficiency USB Power Manager + Triple Step-Down DC/DC
Manufacturer
Linear Technology
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LTC3555EUFD
Manufacturer:
LT
Quantity:
10 000
Part Number:
LTC3555EUFD
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC3555EUFD#PBF
Manufacturer:
LINEAR
Quantity:
2 065
Part Number:
LTC3555EUFD#TRPBF
Manufacturer:
LT
Quantity:
1 875
Part Number:
LTC3555EUFD#TRPBF
Manufacturer:
ALLEGRO
Quantity:
1 200
Part Number:
LTC3555EUFD#TRPBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Company:
Part Number:
LTC3555EUFD#TRPBF
Quantity:
519
Part Number:
LTC3555EUFD-1
Manufacturer:
LT
Quantity:
10 000
Part Number:
LTC3555EUFD-1
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC3555EUFD-1#PBF
Manufacturer:
LINEAR/凌特
Quantity:
20 000
Part Number:
LTC3555EUFD-1#TRPBF
Manufacturer:
LT/凌特
Quantity:
20 000
www.DataSheet4U.com
APPLICATIONS INFORMATION
Furthermore, due to its high frequency switching circuitry,
it is imperative that the input capacitors, inductors and
output capacitors be as close to the LTC3555 as possible
and that there be an unbroken ground plane under the
LTC3555 and all of its external high frequency compo-
nents. High frequency currents, such as the V
V
way along the ground plane in a myriad of paths ranging
from directly back to a mirror path beneath the incident
path on the top of the board. If there are slits or cuts
in the ground plane due to other traces on that layer,
the current will be forced to go around the slits. If high
frequency currents are not allowed to fl ow back through
their natural least-area path, excessive voltage will build
up and radiated emissions will occur. There should be a
group of vias under the grounded backside of the pack-
age leading directly down to an internal ground plane. To
minimize parasitic inductance, the ground plane should
be on the second layer of the PC board.
The GATE pin for the external ideal diode controller has
extremely limited drive current. Care must be taken to
minimize leakage to adjacent PC board traces. 100nA of
leakage from this pin will introduce an offset to the 15mV
ideal diode of approximately 10mV. To minimize leakage,
the trace can be guarded on the PC board by surrounding
it with V
less that one volt higher than GATE.
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3555.
IN2
Figure 7. Higher Frequency Ground Currents Follow Their
Incident Path. Slices in the Ground Plane Cause High Voltage
and Increased Emissions
and V
OUT
IN3
connected metal, which should generally be
currents on the LTC3555, tend to fi nd their
3555 F07
BUS
, V
IN1
,
1. Are the capacitors at V
as possible to the LTC3555? These capacitors provide
the AC current to the internal power MOSFETs and their
drivers. Minimizing inductance from these capacitors to
the LTC3555 is a top priority.
2. Are C
C
3. Keep sensitive components away from the SW pins.
Battery Charger Stability Considerations
The LTC3555’s battery charger contains both a constant-
voltage and a constant-current control loop. The constant-
voltage loop is stable without any compensation when a
battery is connected with low impedance leads. Excessive
lead length, however, may add enough series inductance
to require a bypass capacitor of at least 1μF from BAT to
GND. Furthermore, when the battery is disconnected, a
4.7μF capacitor in series with a 0.2Ω to 1Ω resistor from
BAT to GND is required to keep ripple voltage low.
High value, low ESR multilayer ceramic chip capacitors
reduce the constant-voltage loop phase margin, possibly
resulting in instability. Ceramic capacitors up to 22μF may
be used in parallel with a battery, but larger ceramics should
be decoupled with 0.2Ω to 1Ω of series resistance.
In constant-current mode, the PROG pin is in the feed-
back loop rather than the battery voltage. Because of the
additional pole created by any PROG pin capacitance,
capacitance on this pin must be kept to a minimum. With
no additional capacitance on the PROG pin, the battery
charger is stable with program resistor values as high
as 25k. However, additional capacitance on this node
reduces the maximum allowed program resistor. The pole
frequency at the PROG pin should be kept above 100kHz.
Therefore, if the PROG pin has a parasitic capacitance,
C
the maximum resistance value for R
OUT
PROG
R
PROG
returns current to the GND plane.
, the following equation should be used to calculate
OUT
2
and L1 closely connected? The (–) plate of
π •
100
kHz C
1
BUS
, V
PROG
IN1
, V
IN2
PROG
LTC3555
and V
:
IN3
as close
29
3555f

Related parts for LTC3555