LTC3835 Linear Technology, LTC3835 Datasheet - Page 19

• Manufacturer Part Number: LTC3835
• Description: Low IQ Synchronous Step-Down Controller
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3835 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET (TG)
to be locked to the rising edge of an external clock signal
applied to the PLLIN/MODE pin. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of comple-
mentary current sources that charge or discharge the
external fi lter network connected to the PLLLPF pin. The
relationship between the voltage on the PLLLPF pin and
operating frequency, when there is a clock signal applied
to PLLIN/MODE, is shown in Figure 7 and specifi ed in the
Electrical Characteristics table. Note that the LTC3835 can
only be synchronized to an external clock whose frequency
is within range of the LTC3835’s internal VCO, which is
nominally 115kHz to 800kHz. This is guaranteed to be
between 140kHz and 650kHz. A simplifi ed block diagram
is shown in Figure 8.
If the external clock frequency is greater than the internal
oscillator’s frequency, f
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
Figure 7. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
900
800
700
600
500
400
300
200
100
0
0
0.5
PLLLPF PIN VOLTAGE (V)
OSC
, then current is sourced con-
1
1.5
2
3835 F07
2.5
than f
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. The voltage on the PLLLPF pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the fi lter capacitor C
The loop fi lter components, C
current pulses from the phase detector and provide a stable
input to the voltage-controlled oscillator. The fi lter compo-
nents C
lock. Typically R
Typically, the external clock (on PLLIN/MODE pin) input high
threshold is 1.6V, while the input low threshold is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN
0V
Floating
INTV
RC Loop Filter
OSCILLATOR
EXTERNAL
CC
OSC
LP
Figure 8. Phase-Locked Loop Block Diagram
, current is sunk continuously, pulling down
and R
PLLIN/
MODE
LP
PLLIN/MODE PIN
LP
Clock Signal
DC Voltage
DC Voltage
DC Voltage
= 10k and C
determine how fast the loop acquires
FREQUENCY
LP
DETECTOR
DIGITAL
PHASE/
holds the voltage.
LP
LP
Phase-Locked to External Clock
and R
is 2200pF to 0.01μF .
2.4V
LP
FREQUENCY
LTC3835
, smooth out the
250kHz
400kHz
530kHz
PLLLPF
R
LP
OSCILLATOR
19
3835 F08
C
3835fc
LP