LTC4217 Linear Technology, LTC4217 Datasheet - Page 13

• Manufacturer Part Number: LTC4217
• Description: 2A Integrated Hot Swap Controller
• Manufacturer: Linear Technology

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APPLICATIONS INFORMATION
12V Fixed Version
In the LTC4217-12 the UV, OV and FB pins are driven by
internal dividers which may need to be fi ltered to prevent
false faults. By placing a bypass capacitor on these pins
the faults are delayed by the RC time constant. Use the R
value from the electrical table for this calculation.
In cases where the fi xed thresholds need a slight adjust-
ment, placing a resistor from the UV or OV pins to V
or GND will adjust the threshold up or down. Likewise
placing a resistor between FB pin to OUT or GND adjusts
the threshold. Again use the R
table for this calculation.
An example in Figure 5 raises the UV turn-on voltage from
9.88V to 10.5V. Increasing the UV level requires adding a
resistor between UV and ground. The resistor, R
can be calculated using electrical table parameters as
follows:
In this same fi gure the OV threshold is lowered from
15.05V to 13.5V. Decreasing the OV threshold requires
adding a resistor between V
be calculated as follows:
R
R
18
SHUNT
SHUNT
k
1 235
.
•
15 05
Figure 5. Adjusting LTC4217-12 Thresholds
1
2
.
=
=
(
R
V
⎛
⎜
⎝
R
( )
NEW
IN
(
(
( )
13 5 1 235
1 1 5 05 13 5
V
IN
( )
•
TH
. – .
.
LTC4217-12
•
–
V
V
OLD
V
OLD
–
OLD
⎛
⎜
⎜
⎜
⎝
4217 F05
DD
)
(
.
V
=
(
IN
)
)
NEW
V
OV
UV
V
and OV. This resistor can
DD
⎞
⎟ =
⎠
(
OLD
value from the electrical
10 5
18
1 736
R
R
. – 9 9 88
–
k
SHUNT2
SHUNT1
–
.
V
• .
V
OV TH
9 88
N N EW
.
( )
M
)
)
)
=
⎞
⎟
⎟
⎟
⎠
287
=
SHUNT1
k
DD
IN
,
The inrush current is defi ned by the current required to
charge the output capacitor using the fi xed 0.3V/ms GATE
charge up rate. The inrush current is defi ned as:
As mentioned previously the charge up time is the out-
put voltage (12V) divided by the output rate of 0.3V/ms
resulting in 40ms. The peak power dissipation of 12V at
100mA (or 1.2W) is within the SOA of the pass MOSFET
for 40ms (see MOSFET SOA curve in the Typical Perfor-
mance Characteristics).
Next the power dissipated in the MOSFET during overcurrent
must be limited. The active current limit uses a timer to
prevent excessive energy dissipation in the MOSFET. The
worst-case power dissipation occurs when the voltage
versus current profi le of the foldback current limit is at
the maximum. This occurs when the current is 2A and the
voltage is one half of the 12V or 6V. See the Current Limit
Sense Voltage vs FB Voltage in the Typical Performance
Characteristics section to view this profi le. In order to
survive 12W, the MOSFET SOA dictates a maximum time
of 10ms (see SOA graph). Use the internal 2ms timer
Use the equation for R
FB thresholds. Likewise use the equation for R
decreasing the UV and FB thresholds.
Design Example
Consider the following design example (Figure 6): V
12V, I
9.88V, V
triggers an automatic restart of the power up sequence.
12V
I
INRUSH
MAX
OVOFF
Figure 6. 1.5A, 12V Card Resident Application
= 2A. I
=
C
= 15.05V, V
L
•
⎛
⎝ ⎜
INRUSH
0.1μF
0 3
ms
C1
.
V
SHUNT1
PWRGD
⎞
⎠ ⎟
= 100mA, C
=
V
UV
FLT
TIMER
INTV
LTC4217-12DHC
DD
330
CC
for increasing the OV and
= 10.5V. A current limit fault
GND
µF
I
•
OUT
MON
PG
⎛
⎝ ⎜
L
0 3
ms
.
= 330μF , V
12V
LTC4217
V
R1
10k
R2
20k
⎞
⎠ ⎟
+
=
SHUNT2
1 1 00mA
C
330μF
L
13
UVON
ADC
4217fb
V
12V
1.5A
IN
OUT
4217 F06
for
=
=