LTC4260 Linear Technology, LTC4260 Datasheet - Page 10

• Manufacturer Part Number: LTC4260
• Description: Positive High Voltage Hot Swap Controller
• Manufacturer: Linear Technology

OPERATIO
LTC4260
The Functional Diagram displays the main functional areas
of this device. The LTC4260 is designed to turn a board’s
supply voltage on and off in a controlled manner, allowing
the board to be safely inserted or removed from a live
backplane. During normal operation, the charge pump and
gate driver turn on the external N-channel pass FET’s gate
to pass power to the load. The gate driver uses a charge
pump that derives its power from the SOURCE pin. When
the SOURCE pin is at ground, the charge pump is powered
from an internal 12V supply derived from V
in a 200µA current load on the SOURCE pin when the gate
is up. Also included in the gate driver is an internal 15V
gate-to-source clamp.
The current sense (CS) amplifier monitors the load current
using the difference between the V
voltage. The CS amplifier limits the current in the load by
reducing the GATE-to-SOURCE voltage in an active con-
trol loop. The CS amplifier requires 100µA input bias
current from both the V
A short circuit on the output to ground causes significant
power dissipation during active current limiting. To limit
this power, the foldback amplifier reduces the current limit
value from 50mV to 20mV (referred to the V
SENSE voltage) in a linear manner as the FB pin drops
below 2V (see Typical Performance curves).
If an overcurrent condition persists, the TIMER pin ramps
up with a 100µA current source until the pin voltage
exceeds 1.2V (comparator TM2). This indicates to the
logic that it is time to turn off the pass FET to prevent
overheating. At this point the TIMER pin ramps down
using the 2µA current source until the voltage drops below
TI I G DIAGRA
10
W
U
SDAI/SDAO
t
SCL
HD, STA
U
CONDITION
START
DD
and the SENSE pins.
W
t
SU, DAT
DD
and SENSE pin
DD
. This results
t
t
HD, DATO,
HD, DATI
DD
minus
REPEATED START
CONDITION
0.2V (comparator TM1) which tells the logic that the pass
transistor has cooled and it is safe to turn it on again.
The output voltage is monitored using the FB pin and the
PG comparator to determine if the power is available for
the load. The power good condition is signalled by the
GPIO pin using an open-drain pull-down transistor. The
GPIO pin can also be used as a general purpose input (GP
comparator) or output pin.
The Functional Diagram shows the monitoring blocks of
the LTC4260. The group of comparators on the left side
includes the UV, OV, RST, BP and ON comparators. These
comparators are used to determine if the external condi-
tions are valid prior to turning on the FET. But first the two
undervoltage lockout circuits UVLO1 and UVLO2 must
validate the input supply and the internally generated 5.5V
supply (INTV
the logic circuits.
Included in the LTC4260 is an 8-bit A/D converter. The
converter has a 3-input mux to select between the ADIN
pin, the SOURCE pin and the V
An I
also allows the host to poll the device and determine if
faults have occurred. If the ALERT line is used as an
interrupt, the host can respond to a fault in real time. The
typical SDA line is divided into an SDAI (input) and SDAO
(output). This simplifies applications using an optoisolator
driven directly from the SDAO output. The I
address is decoded using the ADR0, ADR1 and ADR2 pins.
These inputs have three states each that decode into a total
of 27 device addresses.
t
SU, STA
2
C interface is provided to read the A/D registers. It
t
HD, STA
t
SP
t
CC
SP
) and generate the power up initialization to
t
SU, STO
CONDITION
STOP
DD
t
BUF
– SENSE voltage.
CONDITION
START
4260 TD01
2
C device
4260f