MX25L6402 Macronix International, MX25L6402 Datasheet - Page 5

• Manufacturer Part Number: MX25L6402
• Description: 64M-BIT [x 1] CMOS SERIAL eLite FlashTM MEMORY
• Manufacturer: Macronix International

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COMMAND DESCRIPTION
(1) Read Array
This command is sent with the 4-byte address (command included), and the byte address, followed by four dummy bytes
sent to give the device time to stabilize. The device will then send out data starting at the byte address until CS goes
high. The clock to clock out the data is supplied by the master SPI. The read operation is executed on whole array. If
the end of the array is reached then the device will wrap around to the beginning of the array.
(2) Read Status Register
Note 1: The initial value of Bit7 is "1". Bit7 will have "1" to "0" transit only after program/erase operation is completed. Bit7
will shift from "0" to "1" only after issued program/erase/Clear status register command. Please note the Bit7=0 if program/
erase fail.
Note 2: The value of Bit 0 is "1", no matter the result of program/erase is pass or fail.
(3) Clear Status Register
This command only resets erase error bit (bit 4) and program error bit (bit 3) . These two bits are set by on-chip state machine
during program/erase operation, and can only be reset by issuing a clear status register command or by powering down
VCC .
If status register indicates that error occurred in the last program/erase operation, any further program/erase operation will
be prohibited until status register is cleared.
Bit 6,5,2,1 = Reserve for future use.
Bit 4 = "1" -----> There is an error occurred in last erase operation.
Bit 3 = "1" -----> There is an error occurred in last program operation.
Bit 0 ="1" -----> Device is in ready mode.
(4) Read ID
This command is sent with an extra dummy byte( 2-byte command). The device will clock out manufacturer code (C2H)
and device code (9CH) when this command is issued. The clock to clock out the data is supplied by the master SPI.
P/N: PM0943
When this command is sent, the device will continuously send out the status register contents starting at bit7. The clock
to clock out the data is supplied by the master SPI.
DEVICE OPERATION
1.Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2.When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until
3.When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS
bit7
program
completion
Note1
next CS falling edge. In standby mode, SO pin of this LSI should be High-Z.
rising edge.
= "0" -----> There is no error occurred in last erase operation.
= "0" -----> There is no error occurred in last program operation.
="0" -----> Device is in busy mode.
/erase
bit6
NA
bit5
NA
bit4
erase
error
1=error
5
bit3
program
error
1=error
bit2
NA
MX25L6402
bit1
NA
REV. 1.0, SEP. 29, 2004
bit0
ready/busy
1=ready
0=busy