MX25L6402A Macronix International, MX25L6402A Datasheet - Page 19
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MX25L6402A
Manufacturer Part Number
MX25L6402A
Description
64M-BIT [x 1] CMOS SERIAL eLite FlashTM MEMORY
Manufacturer
Macronix International
Datasheet
1.MX25L6402A.pdf
(30 pages)
- Current page: 19 of 30
- Download datasheet (513Kb)
www.DataSheet4U.com
READ STATUS REGISTER TIMING WAVEFORM (Parallel)
P/N: PM1040
NOTES:
1. BIT 7=0 ==> Program/Erase completed
2. BIT 6=0 ==> Device is not in parallel mode
2. BIT 4=1 ==>Erase Error
3. BIT 3=1 ==>Program Error
4. BIT 1,2,5 ==> Reserve for future use
5. Bit 0=1 ==> Device is in ready state
6. Under parallel mode, the fastest access clock freq. will be changed to 1.25MHz(SCLK pin clock freq.).
7. To read status register in parallel mode, which requires a parallel mode command (55H) before the read status register
command.
Once in the parallel mode, eLite Flash
TM
Memory will not exit parallel mode until power-off.
19
MX25L6402A
REV. 1.0, SEP. 29, 2004
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