74LCX374MTCX Fairchild Semiconductor, 74LCX374MTCX Datasheet - Page 7

• Manufacturer Part Number: 74LCX374MTCX
• Description: IC FLIP FLOP OCT D LV 20TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74LCXr
• Type: D-Type Busr

Specifications of 74LCX374MTCX

• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 150MHz
• Delay Time - Propagation: 8.5ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Number Of Circuits: 8
• Logic Family: 74LC
• Logic Type: D-Type Flip-Flop
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 9.5 ns
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Supply Voltage (max): 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 2 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

©2006 Fairchild Semiconductor Corporation
74LCX374 Rev. 1.6.0
AC Loading and Waveforms
CONTROL
CONTROL
OUTPUT
OUTPUT
Propagation Delay. Pulse Width and
DATA
DATA
OUT
CLOCK
3-STATE Output Low Enable and
IN
DATA
OUT
Waveform for Inverting and
IN
Non-Inverting Functions
Disable Times for Logic
t
t
PZL
rec
t
pxx
t
Figure 2. Waveforms (Input Characteristics; f =1MHz, t
Symbol
PHL
Waveforms
Figure 1. AC Test Circuit (C
SIGNAL
TEST
V
V
V
V
V
mo
V
mo
mi
t
x
y
W
mo
t
PLZ
t
pxx
t
V
V
DUT
rec
t
t
V
t
V
CC
PZH
mi
PLH
PZL
V
mi
3.3V ± 0.3V
mi
V
Test
V
mo
(Generic for LCX Family)
V
OH
OL
t
, t
, t
, t
mi
PLH
V
V
GND
1.5V
1.5V
mo
PHL
PLZ
PHZ
CC
+ 0.3V
V
V
– 0.3V
V
GND
V
GND
X
OL
CC
CC
C
L
V
L
CC
6V at V
includes probe and jig capacitance)
500
x 2 at V
7
500
V
V
OH
OL
Switch
CC
2.7V
Open
1.5V
1.5V
GND
V
CC
+ 0.3V
– 0.3V
CC
OUTPUT
3.3 ± 0.3V
CONTROL
ANY
CONTROL
2.5 ± 0.2V
OUTPUT
CLEAR
3-STATE Output High Enable and
INPUT
OPEN
GND
V
DATA
DATA
I
OUT
MR
OR
Setup Time, Hold Time and
IN
Recovery Time for Logic
Disable Times for Logic
2.5V ± 0.2V
V
V
t
t
r
10%
PZH
OH
OL
r
V
V
90%
= t
t
CC
CC
rise
+ 0.15V
– 0.15V
t
t
t
PLH
PZH
PZL
f
/ 2
/ 2
= 3ns)
t
and t
S
V
, t
, t
, t
90%
mo
PLZ
PHL
PHZ
t
S
10%
t
rec
V
fall
t
mi
PHZ
t
f
t
V
H
mi
V
mi
V
mi
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V
V
V
GND
V
GND
V
GND
OH
Y
CC
CC
CC
V
V
OH
OL