cy2hh8110 Cypress Semiconductor Corporation., cy2hh8110 Datasheet

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cy2hh8110

Manufacturer Part Number
cy2hh8110
Description
1.5v 1 10 Hstl Fanout Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07556 Rev **
Features
Block Diagram
• DC to 150-MHz operation
• 1.5V power supply
• One single-ended HSTL input
• Ten single-ended Class II HSTL outputs
• Less than 1.9% Duty Cycle distortion
• Balanced 16-mA output drive
• Output Enable/Disable
• Low output-output skew
• Operating temperature range: 0°C to +85°C
• 32-pin TQFP package
IN
OE
Q 10
Q 1
Q 9
Q 2
3901 North First Street
Pin Configuration
Description
The CY2HH8110 is a low-voltage HSTL fanout buffer
designed for data communications, clock management, and
specialty memory applications.
The class II HSTL outputs are balanced Push-Pull in design
capable of delivering 16 mA into 10 pF load. This class allows
both source series termination and symmetrically double
parallel termination.
The CY2HH8110 low-output duty cycle distortion makes it
suitable for Double Data Rate (DDR) applications.
1.5V 1:10 HSTL Fanout Buffer
G ND
GND
VDD
GND
VDD
VDD
OE
IN
1
2
3
4
5
6
7
8
32
San Jose
9
31
10
CY2HH8110
30
11
,
29
12
CA 95134
28
13
27
14
26
15
Revised August 1, 2003
25
16
23
20
19
18
24
22
17
21
CY2HH8110
408-943-2600
GND
Q 4
Q 5
VDD
VDD
Q 6
Q 7
G ND
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cy2hh8110 Summary of contents

Page 1

... Cypress Semiconductor Corporation Document #: 38-07556 Rev ** 1.5V 1:10 HSTL Fanout Buffer Description The CY2HH8110 is a low-voltage HSTL fanout buffer designed for data communications, clock management, and specialty memory applications. The class II HSTL outputs are balanced Push-Pull in design capable of delivering 16 mA into 10 pF load. This class allows both source series termination and symmetrically double parallel termination ...

Page 2

... HSTL HSTL reference clock input O HSTL HSTL clock outputs I, PD LVCMOS Output enable/disable input. When held LOW, outputs are enabled. When set HIGH, all outputs are disabled LOW. Supply VDD 1.5V power supply Supply Ground Common ground CY2HH8110 Description [2] Page [+] Feedback ...

Page 3

... IN Outputs loaded @ 62.5 MHz [5] = 1.5V ± 8 0°C to +85°C) A Condition V =V /2, Internal Voltage REF DD Reference 20% to 80% Fout < 100 MHz Fout > 100 MHz . Parameters are guaranteed by characterization and are not 100% tested. TT CY2HH8110 Min. Max. Unit –0.5 2.5 V 1.35 1. –0 0.5 V ...

Page 4

... REF DCD @ f = 62.5 MHz REF tjit_D(cc) Figure 1. Cycle-to-Cycle Jitter Input 80% 20% Output 80% 20% tPLH & tPHL Figure 3. Output to Output Skew Figure 4. Output Enable/Disable Time CY2HH8110 [5] Min. Typ. Max. Unit – – |300| ps – – |1.9| % – – 200 ps – ...

Page 5

... VTT = VDDQ / ohm ohm Cload = 10pf [7,8] and CLASS II HSTL AC Test Load Package Type 32-pin TQFP 32-pin TQFP – Tape and Reel CY2HH8110 [7,8] Product Flow Commercial, 0°C to +85°C Page [+] Feedback ...

Page 6

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY2HH8110 51-85063-*B ...

Page 7

... Document History Page Document Title:CY2HH8110 1.5V 1:10 HSTL Fanout Buffer Document Number: 38-07556 REV. ECN No. Issue Date ** 128398 08/04/03 Document #: 38-07556 Rev ** Orig. of Change Description of Change RGL New Data Sheet CY2HH8110 Page [+] Feedback ...

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