cy2v9950 Cypress Semiconductor Corporation., cy2v9950 Datasheet
cy2v9950
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cy2v9950 Summary of contents
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... M 3 Cypress Semiconductor Corporation Document #: 38-07436 Rev. *A Functional Description The CY2V9950 is a low-voltage, low-power, eight-output, 200-MHz clock driver. It features functions necessary to optimize the timing of high performance computer and communication systems. The user can program the output banks through 3F[0:1] and 4F[0:1]pins. Any one of the outputs can be connected to feedback input to achieve different reference frequency multi- plication and divide ratios and zero input-output delay ...
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... VSS Power PWR 28 Device Configuration The outputs of the CY2V9950 can be configured to run at frequencies ranging from 6 to 200 MHz. Banks 3 and 4 output dividers are controlled by 3F[1:0] and 4F[1:0] as indicated in Table 1 and 2 respectively. Table 1. Output Divider Settings – Bank 3 3F[1:0] K – Bank3 Output Divider ...
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... PE Synchronization L H The CY2V9950 features split power supply buses for Banks 1 and 2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V and 2.5V output signals from one device. The core power supply (VDD) must be set a level which is equal or higher than that on any one of the output power supplies. ...
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... mA, (nQ[0:1 –12 mA, (nQ[0:1]) OH VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, outputs not loaded @100 MHz Condition 0.8V – 2.0V HIGH or LOW FS = LOW FS = MID FS = HIGH CY2V9950 µA – 200 µA –50 50 µA –200 – µA –25 – µA – 100 – ...
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... Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD = 2.5V. Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD = 2.5V. Measured at 0.8V – 2.0V for VDD = 3.3V and 0.7V – 1.7V for VDD = 2.5V Divide by 1 output frequency divide Divide by 1 output frequency M/ divide CY2V9950 Min. Max. Unit 6 200 MHz 200 400 MHz ...
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... AC Timing Definitions t PWH REF OTHER Q INVERTED Q REF DIVIDED BY 2 REF DIVIDED BY 4 Document #: 38-07436 Rev REF t PWL t t 0DCV 0DCV t t SKEWPR SKEWPR t SKEW0,1 t SKEW0 SKEW1 SKEW1 t SKEW3 t SKEW3 t SKEW1,3,4 CY2V9950 t CCJ1-12 t SKEW3 t SKEW1,3,4 Page [+] Feedback ...
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... For All Other Outputs Figure 1. t OFALL 1.7V VTH =1.25V 0.7V Figure 2. LVTTL Output Test Waveforms ≤ 1ns 2.5V 1.7V VTH =1.25V 0.7V Figure 3. LVTTL Input Test Waveforms Package Type CY2V9950 150Ω 20pF 150Ω ORISE OFALL t PWH t PWL 2.5V LVTTL OUTPUT WAVEFORM ≤ 1ns ≤ 1ns 0V 2 ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY2V9950 51-85063-B ...
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... Document History Page Document Title:CY2V9950 2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer Document Number: 38-07436 REV. ECN No. Issue Date ** 122628 01/10/03 *A 252355 See ECN RGL/GGK Document #: 38-07436 Rev. *A Orig. of Change Description of Change RGL New Data Sheet Fixed Note 3 definition. CY2V9950 Page [+] Feedback ...