cy2xf23 Cypress Semiconductor Corporation., cy2xf23 Datasheet
cy2xf23
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cy2xf23 Summary of contents
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... Oscillator (XO). It uses a Cypress proprietary low noise PLL to synthesize the frequency from an integrated crystal. The output frequency can be changed using the I allowing easy frequency margin testing in applications. The CY2XF23 is available as a factory configured device field programmable device. CRYSTAL LOW-NOISE OSCILLATOR ...
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... At power on, the device returns to its original state. The configuration for a particular frequency is stored in a 6-byte block of memory, known as a word. The CY2XF23 has four such words, labeled Frequency Word 0 through Frequency Word 3. An additional register byte contains a 2-bit field, which selects one of the four frequency words ...
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... The CY2XF23 uses pins SDA and SCLK for an I operates up to 100 kbits/sec in Read or Write mode. The CY2XF23 is always a slave on this bus, meaning that it never initiates a bus transaction. The basic Write protocol is as follows: Start Bit; 7-bit Device Address (DA); R/W Bit; Slave Clock Acknowledge (ACK) ...
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... Valid Document Number: 001-53145 Rev. *A PRELIMINARY the CY2XF23 receives the slave address with the R/W bit set to a ‘1’, the CY2XF23 issues an acknowledge and transmits the 8-bit word. The master device does not acknowledge the transfer, but does generate a STOP condition, which causes the CY2XF23 to stop transmission ...
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... Transition Data Valid to next Bit CLK HIGH VIH CLK VIL LOW Figure 6. Start and Stop Frame Transition to next Bit STOP CY2XF23 1 Bit 1 Bit 1 Bit Slave Slave Slave ACK ACK ACK 8-bit Register Data (00H) Stop Signal 1 Bit 1 Bit 1 Bit ...
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... Figure terminated in Figure 3.3V or 2.5V, defined in Figure terminated in Figure 3.3V or 2.5V, defined in Figure terminated in Figure 3.3V or 2.5V 100Ω DD TERM between CLK and CLK# CY2XF23 + ACK STOP + Min Max Unit –0.5 4.4 V –0 –55 135 °C –40 135 ° ...
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... Time for CLK to reach valid frequency from serial bus change to select bits in register 2 40h, measured from I C STOP f = 106.25 MHz (12 kHz–20 MHz) OUT . It includes initial accuracy, plus variation from temperature and supply voltage. 0 CY2XF23 Min Typ Max Unit – – 0.1 0.7*V – ...
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... Description Figure 8. Output Voltage Swing CLK# V OD1 CLK Δ OD1 OD2 Figure 9. Output Offset Voltage CLK 50Ω 50Ω CLK# Figure 10. Duty Cycle Timing CLK PERIOD CY2XF23 Min Max 100 4 4.7 4 1000 0 200 300 300 4 4.7 V OD2 ...
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... Figure 11. Output Rise and Fall Time CLK# 80% 80% 20% CLK Figure 12. RMS Phase Jitter Phase noise Noise Power Offset Frequency f2 f1 Area Under the Masked Phase Noise Plot RMS Jitter = Figure 13. LVDS Termination CLK 100Ω CLK# CY2XF23 20% Phase noise mark Page [+] Feedback ...
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... Ceramic LCC SMD - Tape and Reel 6-Pin Ceramic LCC SMD - Tape and Reel 0.64 TYP. TYP. 0.20 R REF BOTTOM VIEW CY2XF23 Product Flow Commercial, 0° to 70°C Industrial, –40° to 85°C Commercial, 0° to 70°C Industrial, –40° to 85°C 2.54 TYP. TYP. 0.10 R REF. 0.32 R ...
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... Document History Page Document Title: CY2XF23 High Performance LVDS Oscillator with Frequency Margining - I2C Control Document Number: 001-53145 Orig. of Submission REV. ECN NO. Change ** 2704379 KVM/PYRS *A 2718898 WWZ Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress ...