cy2dp3120 Cypress Semiconductor Corporation., cy2dp3120 Datasheet

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cy2dp3120

Manufacturer Part Number
cy2dp3120
Description
1 20 Differential Clock/data Fanout Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Cypress Semiconductor Corporation
Document #: 38-07514 Rev.*C
Features
• Twenty ECL/PECL differential outputs
• One ECL/PECL compatible differential or single-ended
• One HSTL compatible differential or single-ended clock
• Hot-swappable/-insertable
• 50 ps output-to-output skew
• 150 ps device-to-device skew
• 500 ps propagation delay (typical)
• 1.4 ps RMS period jitter (max.)
• 1.5 GHz Operation (2.7 GHz max. toggle frequency)
• PECL mode supply range: V
• ECL mode supply range: V
• Industrial temperature range: –40°C to 85°C
• 52-pin 1.4-mm TQFP package
• Temperature compensation like 100K ECL
• Pin compatible with MC100ES6221
Block Diagram
clock inputs
inputs
with V
with V
CLK_SEL
CLKA#
CLKB#
CLKA
CLKB
EE
CC
VCC
= 0V
VCC
= 0V
VEE
VEE
VEE
E E
CC
= –2.5V± 5% to –3.3V±5%
= 2.5V± 5% to 3.3V±5%
1:20 Differential Clock/Data Fanout Buffer
3901 North First Street
Q 0
Q 0#
VBB
Q 19
Q 19#
Functional Description
The CY2DP3120 is a low-skew, low propagation delay 1-to-20
differential fanout buffer targeted to meet the requirements of
high-performance clock and data distribution applications. The
device is implemented on SiGe technology and has a fully
differential internal architecture that is optimized to achieve
low signal skews at operating frequencies of up to 1.5 GHz.
The device features two differential input paths that are multi-
plexed internally. This mux is controlled by the CLK_SEL pin.
The CY2DP3120 may function not only as a differential clock
buffer but also as a signal-level translator and fanout on
ECL/PECL signal to twenty ECL/PECL differential loads. An
external bias pin, VBB, is provided for this purpose. In such an
application, the VBB pin should be connected to either one of
the CLKA# or CLKB# inputs and bypassed to ground via a
0.01-PF capacitor. Traditionally, in ECL, it is used to provide
the reference level to a receiving single-ended input that might
have a different self-bias point.
Since the CY2DP3120 introduces negligible jitter to the timing
budget, it is the ideal choice for distributing high frequency,
high precision clocks across back-planes and boards in
communication systems. Furthermore, advanced circuit
design schemes, such as internal temperature compensation,
ensure that the CY2DP3120 delivers consistent performance
over various platforms.
CLK_SEL
Pin Configuration
CLKA#
CLKB#
CLKA
CLKB
Q19#
Q18#
VCC
VCC
VBB
VEE
Q19
Q18
San Jose
52
10
11
12
13
4
5
6
9
1
2
3
7
8
14
51
15
50
16
,
49
17
CA 95134
CY2DP3120
48
18
47
19
FastEdge™ Series
46
20
45
21
44
22
Revised July 28, 2004
43
23
42
24
CY2DP3120
41
25
408-943-2600
40
26
36
35
34
31
30
28
27
39
38
37
33
32
29
Q6
Q6#
Q7
Q7#
Q8
Q8#
Q9
Q9#
Q10
Q10#
Q11
Q11#
VCC

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cy2dp3120 Summary of contents

Page 1

... The device features two differential input paths that are multi- plexed internally. This mux is controlled by the CLK_SEL pin. The CY2DP3120 may function not only as a differential clock buffer but also as a signal-level translator and fanout on ECL/PECL signal to twenty ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose ...

Page 2

... CLKB, CLKB# input pair is active. CLKB can be driven with HSTL-compatible signals with respective power configurations Governing Agencies The following agencies provide specifications that apply to the CY2DP3120. The agency name and relevant specification is listed below in Table 2. Table 2. Agency Name JEDEC JESD 020B (MSL) JESD 51 (Theta JA) JESD 8– ...

Page 3

... V (AC) impacts the device propagation delay, device and part-to-part skew. Refer to Fig DIF =(V -V )/50; I =(V -V OHMIN OHMIN TT OHMAX OHMAX TT CC FastEdge™ Series CY2DP3120 Min. Max. –0.3 4.6 -4.6 0.3 –65 +150 150 2000 3 50 Min. Max. |200| 100 –40 ...

Page 4

... MHz , See Figure 3 [13] 660 MHz [14] [13] 660 MHz [13] 660 MHz , See Figure 3 660 MHz 50% duty cycle Differential 20% to 80% – PLH PHL FastEdge™ Series CY2DP3120 Min. Max. Unit –2.625 –2.375 V –3.465 –3.135 –1.25 –0.7 V – ...

Page 5

... > Figure 3. ECL/LVPECL Output output pulse skew (|t PD PLH FastEdge™ Series CY2DP3120 |), and output-to-output skew (t ...

Page 6

... Document #: 38-07514 Rev.* Figure 5. CY2DP3120 AC Test Reference " " " " ...

Page 7

... Package Type 52-pin TQFP 52-pin TQFP – Tape and Reel 52-pin TQFP - Lead Free 52-pin TQFP – Tape and Reel - Lead Free FastEdge™ Series CY2DP3120 ...

Page 8

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. FastEdge™ Series CY2DP3120 51-85131-** Page ...

Page 9

... Document History Page Document Title: CY2DP3120 FastEdge™ Series 1:20 Differential Clock/Data Fanout Buffer Document Number: 38-07514 REV. ECN NO. Issue Date ** 122438 12/05/02 *A 125457 04/17/03 *B 229391 See ECN *C 247606 See ECN Document #: 38-07514 Rev.*C Orig. of Change RGL New data sheet RGL Corrected typo Q14 pin 44 in the pin configuration diagram Changed pin #s 1,14,27 and 40 from VCC to VCCO Changed title to FastEdge™ ...

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