cy2sstv855 Cypress Semiconductor Corporation., cy2sstv855 Datasheet

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cy2sstv855

Manufacturer Part Number
cy2sstv855
Description
Differential Clock Buffer/driver
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07459 Rev. *D
Features
• Phase-locked loop (PLL) clock distribution for Double
• 1:5 differential outputs
• External feedback pins (FBINT, FBINC) are used to
• SSCG: Spread Aware™ for electromagnetic
• 28-pin TSSOP package
• Conform to JEDEC DDR specifications
Block Diagram
Data Rate Synchronous DRAM applications
synchronize the outputs to the clock input
interference (EMI) reduction
PWRDWN
CLKINT
CLKINC
FBINC
FBINT
AVDD
Powerdown
and test
logic
PLL
3901 North First Street
YC3
YT1
YT2
YT3
YT0
YC0
YC1
YC2
FBOUTT
FBOUTC
Functional Description
The CY2SSTV855 is a high-performance, very-low-skew,
very-low-jitter zero-delay buffer that distributes a differential
clock input pair (SSTL_2) to four differential (SSTL_2) pairs of
clock outputs and one differential pair of feedback clock
outputs. In support of low power requirements, when
power-down is HIGH, the outputs switch in phase and
frequency with the input clock. When power-down is LOW, all
outputs are disabled to a high-impedance state and the PLL is
shut down.
The device supports a low-frequency power-down mode.
When the input is < 20 MHz, the PLL is disabled and the
outputs are put in the Hi-Z state. When the input frequency is
> 20 MHz, the PLL and outputs are enabled.
When AVDD is tied to ground, the PLL is turned off and
bypassed with the input reference clock gated to the outputs.
The Cypress CY2SSTV855 is Spread Aware and supports
tracking of Spread Spectrum clock inputs to reduce EMI
Differential Clock Buffer/Driver
Pin Configuration
CLKINC
CLKINT
VDDQ
VDDQ
AGND
VDDQ
AVDD
GND
GND
GND
YC0
YC1
YT0
YT1
San Jose
1
2
3
4
5
6
7
8
9
10
11
12
13
14
,
28 pin TSSOP
CA 95134
Revised May 07, 2004
CY2SSTV855
28
27
26
25
24
23
22
21
20
19
18
17
16
15
408-943-2600
YC2
GND
YC3
YT3
VDDQ
PWRDWN
FBINT
FBINC
VDDQ
FBOUTC
FBOUTT
VDDQ
YT2
GND

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cy2sstv855 Summary of contents

Page 1

... MHz, the PLL and outputs are enabled. When AVDD is tied to ground, the PLL is turned off and bypassed with the input reference clock gated to the outputs. The Cypress CY2SSTV855 is Spread Aware and supports tracking of Spread Spectrum clock inputs to reduce EMI Pin Configuration ...

Page 2

... When used as a zero-delay buffer the CY2SSTV855 will likely nested clock tree application. For these applications the CY2SSTV855 offers a differential clock input pair as a PLL reference. The CY2SSTV855 then can lock onto the reference and translate with near zero delay to low-skew outputs. For normal operation, the external feedback differential input, FBINT/C, is connected to the feedback output, FBOUTT/C ...

Page 3

... Y[0:3], FBOUTT YC[0:3], FBOUTC Document #: 38-07459 Rev ‡ (‡ ‡ large number of samples Figure 1. Static Phase Offset t ( ‡ ‡ ) Figure 2. Dynamic Phase Offset tsk(o) Figure 3. Output Skew CY2SSTV855 t n+1 ( ‡ ‡ ‡ ‡ ) Page ...

Page 4

... Figure 4. Half-period Jitter t c( it(cc) Figure 5. Cycle-to-cycle Jitter CY2SSTV855 t (hper_N+ c(n) -t c(n) c(n+ Page ...

Page 5

... 2.5V±5 –40°C to +85°C) DD DDQ A Description AV [12] 20% to 80% of VOD [13] [13] f > 66 MHz f > 66 MHz and is the voltage at which the differential signals must be crossing. DDQ CY2SSTV855 and V should be constrained to the in out < out [4] Min. Typ. ...

Page 6

... PACKAGE WEIGHT 0.16 gms 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] Z28.173 STANDARD PKG. ZZ28.173 LEAD FREE PKG. 28 1.10[0.043] MAX. 0.19[0.007] 0.30[0.012] GAUGE PLANE 0.076[0.003] 0.05[0.002] SEATING 0.15[0.006] PLANE CY2SSTV855 [10, 11] (continued) Min. Typ. Max. Unit 1.5 3.5 6 – – 100 –150 – 150 –150 – ...

Page 7

... Document History Page Document Title: CY2SSTV855 Differential Clock Buffer/Driver Document #: 38-07459 REV. ECN NO. Issue Date ** 117544 09/09/02 *A 122934 12/18/02 *B 124087 04/23/03 *C 215389 See ECN *D 224444 See ECN Document #: 38-07459 Rev. *D Orig. of Change HWT New data sheet RBI Add power up requirements to maximum ratings information RGL ...

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