cy27ee16 Cypress Semiconductor Corporation., cy27ee16 Datasheet - Page 5

• Manufacturer Part Number: cy27ee16
• Description: 1 Pll In-system Programmable Clock Generator With Individual 16k Eeprom
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07440 Rev. *C
Reference Frequency (REF)
The reference frequency can be a crystal or a driven
frequency. For crystals, the frequency range must be between
8 MHz and 30 MHz. For a driven frequency, the frequency
range must be between 1 MHz and 167 MHz (Commercial
Temp.) or 150 MHz (Industrial Temp.).
Using a Crystal as the Reference Input
The input crystal oscillator of the CY27EE16ZE is an important
feature because of the flexibility it allows the user in selecting
a crystal as a reference frequency source. The input oscillator
has programmable gain, allowing for maximum compatibility
with a reference crystal, regardless of manufacturer, process,
performance and quality.
Table 2. Programmable Crystal Input Oscillator Gain Settings
Table 3. Register Map for Input Crystal Oscillator Gain Setting
Crystal Input
Frequency
REF
DIV2N [47H]
CLKOE [09H]
DIV1N [OCH]
DIV1SRC [OCH]
DIV2SRC [47H]
Address
12H
Calculated CapLoad Value
Crystal ESR
(
[42H]
Q
Q+2)
total
FTAAddrSrc(1)
default = 0
15–20 MHz
20–25 MHz
25–30 MHz
8–15 MHz
D7
PFD
[40H], [41H], [42H]
(2(PB+4)+PO)
Figure 2. Basic Block Diagram of CY27EE16ZE PLL
P
total
VCO
FTAAddrSrc(0)
default = 0
30Ω
00
01
01
10
D6
00H – 20H
1
0
0
1
60Ω
01
10
10
10
Programmable Crystal Input Oscillator Gain Settings
The Input crystal oscillator gain (XDRV) is controlled by two
bits in register 12H, and are set according to Table 2. The
parameters controlling the gain are the crystal frequency, the
internal crystal parasitic resistance (ESR, available from the
manufacturer), and the CapLoad setting during crystal
start-up.
Bits 3 and 4 of register 12H control the input crystal oscillator
gain setting. Bit 4 is the MSB of the setting, and bit 3 is the
LSB. The setting is programmed according to Table 2.
All other bits in the register are reserved and should be
programmed LOW. See Table 3 for bit locations and values.
default = 1
XCapSrc
Divider Bank 1
Divider Bank 2
D5
/DIV1N
/DIV2N
/
/
/2
/
4
2
3
30Ω
01
01
10
10
20H – 30H
XDRV(1) XDRV(0)
D4
Switch Matrix
60Ω
Crosspoint
10
10
10
11
CLKSRC
[44H,45H]
[45H,46h]
[44H]
[44H]
[45H]
[46H]
D3
CY27EE16ZE
30Ω
01
10
10
11
D2
0
30H – 40H
CLOCK5
CLOCK6
CLOCK1
CLOCK2
CLOCK3
CLOCK4
Page 5 of 17
D1
0
60Ω
N/A
10
10
11
D0
0
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