cy29653 Cypress Semiconductor Corporation., cy29653 Datasheet

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cy29653

Manufacturer Part Number
cy29653
Description
3.3v 125-mhz 8-output Zero Delay Buffer
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Cypress Semiconductor Corporation
Document #: 38-07477 Rev. *C
Features
Block Diagram
• Output frequency range: 25 MHz to 125 MHz
• Input frequency range (
• Input frequency range (
• 30 ps typical peak cycle-to-cycle jitter
• 30 ps typical out-to-output skew
• 3.3V operation
• Eight Clock outputs: Drive up to 16 clock lines
• One feedback output
• LVPECL reference clock input
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9653 and MPC953
• Industrial temperature range: –40°C to +85°C
• 32-pin 1.0-mm TQFP package
PECL_CLK#
PECL_CLK
VCO_SEL
BYPASS#
MR/OE#
PLL_EN
FB_IN
Detector
Phase
LPF
200-500MHz
VCO
÷
÷
4): 35 MHz to 125 MHz
8): 25 MHz to 62.5 MHz
÷2
3.3V 125-MHz 8-Output Zero Delay Buffer
÷4
3901 North First Street
FB_OUT
Q(0:6)
Q7
Description
The CY29653 is a low-voltage high-performance 125-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications. The CY29653 features an LVPECL
reference clock input and provides eight outputs plus one
feedback output. VCO output divides by four or eight per
VCO_SEL
LVCMOS-compatible output can drive 50Ω series- or
parallel-terminated transmission lines. For series-terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:16.
The PLL is ensured stable given that the VCO is configured to
run between 140 MHz to 500 MHz. This allows a wide range
of output frequencies from 25 MHz to 125 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider (see the Frequency Table).
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply. When BYPASS# is set LOW, PLL and output dividers
are bypassed resulting in a 1:9 LVPECL to LVCMOS high
performance fanout buffer. For normal PLL operation both
PLL_EN and BYPASS# are set HIGH.
Pin Configuration
P E C L _ C L K
A V D D
F B _ IN
A V S S
setting
N C
N C
N C
N C
San Jose
1
2
3
4
5
6
7
8
(see
C Y 2 9 6 5 3
,
CA 95134
the
Revised April 13, 2004
Function
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
Q 1
V D D Q
Q 2
V S S
Q 3
V D D Q
Q 4
V S S
408-943-2600
Table).
CY29653
Each
[+] Feedback

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cy29653 Summary of contents

Page 1

... Cypress Semiconductor Corporation Document #: 38-07477 Rev. *C 3.3V 125-MHz 8-Output Zero Delay Buffer Description The CY29653 is a low-voltage high-performance 125-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29653 features an LVPECL reference clock input and provides eight outputs plus one feedback output ...

Page 2

... Input Clock * 4 35 MHz to 125 MHz Input Clock * 8 25 MHz to 62.5 MHz 0 VCO ÷ 2 PLL enabled. The VCO output connects to the output dividers Selects the output dividers Outputs disabled (three-state), VCO running at its minimum frequency CY29653 Description [2] [2] [2] Input Frequency Range 1 Page [+] Feedback ...

Page 3

... Outputs loaded @ 100 MHz [3] = operating temperature range) A Condition ÷4 Feedback ÷8 Feedback Bypass mode (BYPASS LVPECL . Parameters are guaranteed by characterization and are not 100% tested Alternatively, each output drives up to two 50 Ω series terminated TT CY29653 Min. Max. Unit –0.3 5.5 V 3.135 3.465 V –0 0.3 ...

Page 4

... Feedback ohm ohm ohm T VTT Figure 1. AC Test Reference PECL_CLK V CMR PECL_CLK VDD Qn VDD/2 GND Figure 3. Propagation Delay impacts static phase offset t(φ). PP CY29653 [3] Min. Typ. Max. Unit 1.2 – VDD – 0 – 125 MHz 25 – 62.5 45 – ...

Page 5

... TQFP – Tape and Reel CY29653AI 32-pin TQFP CY29653AIT 32-pin TQFP – Tape and Reel Document #: 38-07477 Rev. *C VDD VDD/2 GND Figure 5. Output-to-Output Skew t Package Type CY29653 VDD VDD/2 GND VDD VDD/2 GND t SK(O) sk(O) Product Flow Commercial, 0°C to +70°C Commercial, 0° ...

Page 6

... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY29653 51-85063-*B ...

Page 7

... Document History Page Document Title:CY29653 3.3V 125-MHz 8-Output Zero Delay Buffer Document Number: 38-07477 REV. ECN No. Issue Date ** 126715 05/15/03 *A 130841 11/07/03 *B 209720 See ECN *C 346654 See ECN Document #: 38-07477 Rev. *C Orig. of Change Description of Change RGL New Data Sheet RGL Added Industrial Temp. Range ...

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