cy29773 Cypress Semiconductor Corporation., cy29773 Datasheet
cy29773
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cy29773 Summary of contents
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... The CY29773 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29773 features one LVPECL and two LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each. Each bank divides the VCO output per SEL(A:C) settings (see Table 2 ...
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... Power supply for bank A output clocks. VDD 2.5V or 3.3V Power supply for bank B output clocks. VDD 2.5V or 3.3V Power supply for bank C output clocks. VDD 2.5V or 3.3V Power supply for PLL. VDD 2.5V or 3.3V Power supply for core and inputs. Ground Analog Ground. Ground Common Ground. CY29773 [2,3] [2,3] [2,3] [2,3] [2,3] Page [+] Feedback ...
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... QB(0:3) ÷8 ÷12 ÷16 ÷20 ÷4 ÷6 ÷8 ÷10 CY29773 Input Frequency Range (AVDD = 2.5V) 6.25 MHz to 11.8 MHz 1 SELC0 QC(0:3) ÷4 0 ÷8 1 ÷ ³16 ÷2 0 ÷4 1 ÷6 0 ÷8 1 Page [+] Feedback ...
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... Document #: 38-07573 Rev. *A FB_OUT ÷8 0 ÷12 1 ÷16 0 ÷20 1 ÷16 0 ÷24 1 ÷32 0 ÷40 1 ÷4 0 ÷6 1 ÷8 0 ÷10 1 ÷8 0 ÷12 1 ÷16 0 ÷20 1 CY29773 Page [+] Feedback ...
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... A Condition LVCMOS LVCMOS LVPECL [4] LVPECL – Alternatively, each output drives up to two 50Ω series terminated transmission TT CY29773 Min. Max. Unit –0.3 5.5 V 2.375 3.465 V –0 0 –0 0 ÷ 200 – ...
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... MHz MAX f > 100 MHz MAX 0.6V to 1.8V TCLK to FB_IN PCLK to FB_IN . Outputs are at same supply voltage unless otherwise stated. Parameters are guaranteed impacts static phase offset t(φ). CMR PP CY29773 Min. Typ. Max. Unit µA – – 100 – – ...
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... Condition ÷4 Feedback ÷6 Feedback ÷8 Feedback ÷10 Feedback ÷12 Feedback ÷16 Feedback ÷20 Feedback ÷24 Feedback ÷32 Feedback ÷40 Feedback Bypass mode (PLL_EN = 0) LVPECL LVPECL 0.8V to 2.0V CY29773 Min. Typ. Max. Unit – – – – 100 – – 150 – ...
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... SYNC Output In situations where output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system synchronization. The CY29773 monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs ...
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... QA QC SYNC Power Management The individual output enable/freeze control of the CY29773 allows the user to implement unique power management schemes into the design. The outputs are stopped in the logic ‘0’ state when the freeze control bits are activated. The serial input register contains one programmable freeze enable bit for 12 of the 14 output clocks ...
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... Document #: 38-07573 Rev D10 D11 Figure ohm ohm T VTT ohm ohm ohm T VTT t(φ) t(φ) CY29773 ohm ohm T VTT = 3.3V/2. ohm ohm T VTT = 3.3V/2.5V V CMR VDD VDD/2 GND ...
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... P GND 100% Figure 7. Output Duty Cycle (DC) t SK(O) Figure 8. Output-to-Output Skew, t sk(O) Package Type CY29773 VDD VDD/2 GND VDD VDD/2 GND Product Flow Industrial, –40°C to +85°C Industrial, –40°C to 85°C Industrial, –40°C to +85°C Industrial, –40°C to 85°C ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY29773 51-85158-** ...
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... Document History Page Document Title:CY29773 2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer Document Number: 38-07573 REV. ECN No. Issue Date ** 129007 09/02/03 *A 404290 See ECN Document #: 38-07573 Rev. *A Orig. of Change Description of Change RGL New Data Sheet RGL Added pb-free devices added typical data for period jitter ...