cy24c01 Cypress Semiconductor Corporation., cy24c01 Datasheet - Page 3

• Manufacturer Part Number: cy24c01
• Description: 1 Kbit, 2 Kbit, 4 Kbit, 8 Kbit, And 16 Kbit X8 Two Wire I2c Serial Eeprom
• Manufacturer: Cypress Semiconductor Corporation.

Memory Organization
CY24C01
Internally organized with eight pages of 16 bytes each, the 1K
requires a 7-bit data word address for random word addressing.
CY24C02
Internally organized with 16 pages of 16-bytes each, the 2K
requires a 8-bit data word address for random word addressing.
CY24C04
Internally organized with 32 pages of 16 bytes each, the 4K
requires a 9-bit data word address for random word addressing.
CY24C08
Internally organized with 64 pages of 16 bytes each, the 8K
requires a 10-bit data word address for random word addressing.
CY24C16
Internally organized with 128 pages of 16 bytes each, the 16K
requires an 11-bit data word address for random word
addressing.
Device Operating Features
Clock and Data Transitions
The SDA pin is normally pulled high with an external device. Data
on the SDA pin changes only during SCL low time periods. Data
changes during SCL high periods indicate a start or stop
condition as defined in the following section.
Start Condition
A high to low transition of SDA with SCL high is a start condition
which must precede any other command (see
Table 2. Write Protect
Document #: 001-15632 Rev. *C
S D A
S C L
WP Pin Status
V
V
CC
SS
S T A R T B IT
Full 1K Array
CY24C01
Figure
Figure 2. Start/Stop Definition
2).
Full 2K Array
CY24C02
Part of the Memory Protected
Normal Read/Write Operations
Stop Condition
A low to high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command places the EEPROM
in a standby power mode (see
Acknowledge
All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM acknowledges each
word received by sending a zero during the ninth clock cycle.
Standby Mode
The CY24C01/02/04/08/16 features a low power standby mode,
which is enabled on power up, after the receipt of the STOP bit
and the completion of any internal operations.
Device Internal Reset
To prevent inadvertent write operations during power up, a
Power On Reset (POR) circuit is included. During power up
(continuous rise of V
instruction until the V
threshold is lower than the V
defined in
has passed over the POR threshold, the device is reset and is in
standby power mode. During power down (continuous decay of
V
below the POR threshold voltage, the device stops responding
to any instruction sent to it. Before selecting and issuing instruc-
tions to the memory, a valid and stable V
applied. This voltage must remain stable and valid until the end
of the transmission of the instruction and, for a write instruction,
until the completion of the internal write cycle (t
Memory Reset
After an interruption in protocol, power loss, or system reset, any
two-wire part is reset with the following steps:
1. Clock up to nine cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition as SDA is high.
CC
), when V
Full 4K Array
CY24C04
DC Electrical Characteristics
CC
drops from the normal operating voltage to
CC
CC
reaches the POR threshold voltage (this
), the device does not respond to any
Full 8K Array
CY24C01/02/04/08/16
CY24C08
Figure
CC
minimum operating voltage
2).
S T O P B IT
on page 8). When V
CC
Full 16K Array
voltage must be
WR
CY24C16
).
Page 3 of 16
CC
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