cy241v08a-11 Cypress Semiconductor Corporation., cy241v08a-11 Datasheet - Page 3

• Manufacturer Part Number: cy241v08a-11
• Description: Mpeg Clock Generator With Vcxo
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07654 Rev. *A
Absolute Maximum Conditions
Supply Voltage (V
DC Input Voltage...................................... –0.5V to V
Storage Temperature (Non-condensing)..... –55°C to +125°C
Junction Temperature ................................ –40°C to +125°C
Pullable Crystal Specifications
Recommended Operating Conditions
DC Electrical Specifications
AC Electrical Specifications
F
C
R
R
DL
F
F
C
C
C
VDD
T
C
t
I
I
C
V
f
I
DC
ER
EF
t
t
Notes:
Parameter
Parameter
PU
OH
OL
∆XO
VDD
9
10
1.
2.
3.
NOM
3SEPHI
3SEPLO
A
Parameter
VCXO
LNOM
1
3
0
0
1
LOAD
IN
/R
/C
Crystals that meet this specification include: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI
HA13500XFSA14XC.
–115/+115 ppm assumes 2.5pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less
board capacitance.
Not 100% tested.
[2]
1
1
Parameter
[3]
Nominal crystal frequency
Nominal load capacitance
Equivalent series resistance (ESR)
Ratio of third overtone mode ESR to
fundamental mode ESR
Crystal drive level
Third overtone separation from 3*F
Third overtone separation from 3*F
Crystal shunt capacitance
Ratio of shunt to motional capacitance
Crystal motional capacitance
Output HIGH Current
Output LOW Current
Input Capacitance
VCXO Input Range
VCXO Pullability Range
Supply Current
Output Duty Cycle
Rising Edge Rate
Falling Edge Rate
Clock Jitter
PLL Lock Time
DD
) ........................................–0.5 to +7.0V
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Power-up time for all V
(power ramps must be monotonic)
Description
Name
Name
(V
DD
[1]
= 3.3V)
DD
V
V
Except XIN, XOUT pins
Low Side
High Side
OH
OL
NOM
NOM
Duty Cycle is defined in Figure 1, 50% of V
Output Clock Edge Rate, Measured from 20%
to 80% of V
Output Clock Edge Rate, Measured from 80%
to 20% of V
Peak-to-peak period jitter
pins to reach minimum specified voltage
= 0.5V, V
[3]
= V
Description
DD
Parallel resonance, fundamental mode, AT cut
Fundamental mode
Ratio used because typical R
less than the maximum spec
No external series resistor assumed
High side
Low side
DD
+ 0.5
– 0.5V, V
Description
DD
DD
DD
= 3.3V
, C
, C
LOAD
LOAD
Description
Data Retention @ Tj = 125°C................................> 10 years
Package Power Dissipation...................................... 350 mW
ESD (Human Body Model) MIL-STD-883................. > 2000V
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
DD
= 3.3V
Comments
= 15 pF. See Figure 2.
= 15 pF. See Figure 2.
1
values are much
Min.
115
12
12
–
–
0
–
DD
3.135
Min.
0.05
0
–
Min.
0.8
0.8
45
–
–
Typ.
Min.
14.4
CY241V08A-11
150
300
180
24
24
30
–
–
–
–
–
–
–
3
–
–
Typ.
3.3
Typ.
–
–
–
1.4
1.4
50
–
–
13.5
Typ. Max. Unit
14
18
–
–
–
–
–
–
–
Max.
–115
V
35
–
–
7
–
DD
3.465
Max.
Max.
100
500
55
70
15
–150 ppm
–
–
3
Page 3 of 6
21.6
250
25
–
–
–
–
–
7
Unit
ppm
ppm
mA
mA
mA
pF
V/ns
V/ns
Unit
V
MHz
ppm
Unit
ms
µW
ps
ms
%
pF
pF
°C
pF
fF
Ω
V
–
–
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