cy28508 SpectraLinear Inc, cy28508 Datasheet - Page 2

• Manufacturer Part Number: cy28508
• Description: 333 Mhz Low-voltage Differential Sscg
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 24, 2006
Pin Description
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initialize to their default setting upon power-up, and therefore
use of this interface is optional.
Note:
1
3
4
27, 23, 19
26, 22, 18
6
11
12
14
9
10
16
15
28, 24, 20
25, 21, 17
2
5
7
8
13
1. Throughout this document logic 0 and logic 1 state signals are referenced. As a clarification it should be understood that 1 = high and 0 = low voltage levels. These
levels are defined in the DC Electrical Specifications of this data sheet.
Pin
REF
XIN
XOUT
CPUT[0:2]
CPUC[0:2]
FSEL
SDATA
SCLK
CPU_STOP#
ADDRSEL
LOCK
VDDA
VSSA
VDDQ
VSSQ
VDDX
VSSX
VDDC
VSSC
VDD
Name
[1]
O
I
O
O
O
I, PU
250KΩ
I/O
I
I, PU
250KΩ
I, PD
250KΩ
Open
Drain
PWR
GND
PWR
GND
PWR
GND
PWR
GND
PWR
Type
VDDX Reference Clock. 3.3V 14.318-Mz clock output.
VDDX Crystal Connection or External Reference Frequency Input. This pin has
VDDX Crystal Connection. Connection for an external 14.318-MHz crystal output.
VDDQ CPUT Clock Outputs: Differential True CPU clock outputs.
VDDQ CPUC Clock Outputs: Differential Complementary CPU clock outputs.
VDD
VDD
VDD
VDD
VDD
VDD
Power
dual functions. It can be used as an external 14.318-MHz crystal connection
or as an external reference frequency input.
3.3V LVTTL input for CPU frequency selection.
0 = M&N register set 0, 1 = M&N register set 1.
I
I
CPU stop. 1 = CPUT/C running, 0 = CPUT stopped synchronously low and
CPUC stopped synchronously high. REF remains running.
I
It is recommended that an external 10KΩ resistor is connected to this pin.
With this resistor, 1 = Signifies the VCO has locked onto the target frequency.
0 = Not locked to the designated M&N register pair target frequency.
3.3V power supply for analog PLL.
Ground for analog PLL.
2.5V power supply for output buffers.
Ground for output buffers.
3.3V power supply for oscillator.
Ground for oscillator.
3.3V power supply for core.
Ground for core.
3.3V power supply.
2
2
2
C-compatible SDATA.
C-compatible SCLOCK.
C address selection. 0 = D2, 1 = D4.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1. The block write and block read
protocol is outlined in Table 2 while Table 3 outlines the corre-
sponding byte write and byte read protocol. The Byte Count
value returned is 09h.
The slave receiver address is either D2 or D4, depending on
the state of the ADDRSEL pin.
Description
CY28508
Page 2 of 13