cy28rs680-2 SpectraLinear Inc, cy28rs680-2 Datasheet - Page 9

• Manufacturer Part Number: cy28rs680-2
• Description: Clock Generator For Ati Rs5xx/6xx Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 22, 2006
Byte 16: Overclocking support Register (continued)
Table 4. Crystal Recommendations
Crystal Recommendations
The CY28RS680-2 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28RS680-2 to operate at the wrong frequency and violate
the ppm specification. For most applications there is a
300-ppm frequency shift between series and parallel crystals
due to incorrect loading.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
14.31818 MHz
Frequency
Bit
6
5
4
3
2
1
0
(Fund)
Figure 1. Crystal Capacitive Clarification
@Pup
1
0
0
0
0
0
0
Cut
AT
Watchdog Autorecovery Watchdog Autorecovery Mode
Loading Load Cap
Parallel
Prog_ATIG_EN
Prog_SRC_EN
Prog_CPU_EN
Recovery_N8
FS[C:A]
DF_EN
Name
INFORMATION
20 pF
ADVANCE
0.1 mW
(max.)
FS_override
0 = Select operating frequency by FS[C:A] input pins
1 = Select operating frequency by FSEL[C:A] register values
Dynamic Frequency enable for CPU frequencies
0 = Disable, 1 = Enable
Enables the setting of SRC_PLL (PLL3) N values via byte 8
0 = Disable, 1 = Enable
Enables the setting of ATIG_PLL (PLL2) N values via byte 17
0 = Disable, 1 = Enable
Enables the setting of CPU_PLL (PLL1) M and N values via byte 15 and 16
0 = Disable, 1 = Enable
0 = Disable (manual), 1 = Enable (Auto)
CPU Safe recovery bit 8 for RESET_IN and Watchdog timer timeout.
Drive
Shunt Cap
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
(max.)
5 pF
Cs1
Motional
0.016 pF
Figure 2. Crystal Loading Example
(max.)
Ce1
X1
C i1
Description
C lock C hip
XTAL
Tolerance
35 ppm
(max.)
Ci2
X2
CY28RS680-2
C e2
Stability
30 ppm
(max.)
Cs2
Page 9 of 16
3 to 6p
33 pF
Pin
Trim
2.8 pF
Trace
(max.)
Aging
5 ppm