cy28442-2 Cypress Semiconductor Corporation., cy28442-2 Datasheet - Page 12

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cy28442-2

Manufacturer Part Number
cy28442-2
Description
Clock Generator For Intel Alviso Chipset
Manufacturer
Cypress Semiconductor Corporation.
Datasheet
Document #: 38-07691 Rev. *B
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
CPUC(Free Running
CPUT(Free Running
CPUC(Stoppable)
CPUT(Stoppable)
CPUC(Free Running)
CPUT(Free Running)
CPU_STOP#
CPUC(Stoppable)
CPUT(Stoppable)
CPUC Internal
CPUT Internal
CPU_STOP#
CPU_STP#
DOT96C
DOT96T
DOT96T
DOT96C
CPUT
CPUC
PD
PD
Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state
Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
Figure 7. CPU_STP# Deassertion Waveform
Tdrive_CPU_STP#,10nS>200mV
1.8mS
CY28442-2
1.8mS
Page 12 of 21
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