cy28416 Cypress Semiconductor Corporation., cy28416 Datasheet
cy28416
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cy28416 Summary of contents
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... VDD_48MHz PCI3 DOT96T VSS_PCI DOT96C VDD_PCI 48MHz0 PCIF0/TESTSEL 48MHz1 PCIF1/ITPEN VDD_48 48MHz0/FS_B 48MHz1 VSS_48 DOT96T DOT96C • 3901 North First Street • San Jose CY28416 ® Architecture PCI DOT USB REF VSS_CPU 2 47 CPUT0 3 46 CPUC0 ...
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... LVTTL Input. This pin is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL, and PCIF0/ITP_EN Inputs. After asserting VTT_PWRGD# (active LOW), this pin becomes a realtime input for asserting power-down (active HIGH) I 14.318-MHz Crystal Input O 14.318-MHz Crystal Output CY28416 Description Page [+] Feedback ...
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... Command Code – 8 Bits 19 Acknowledge from slave 20 Repeat start 27:21 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 37:30 Byte Count from slave – 8 bits 38 Acknowledge CY28416 DOT96 USB 96 MHz 48 MHz 96 MHz 48 MHz 96 MHz 48 MHz 96 MHz 48 MHz 96 MHz 48 MHz Description Page ...
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... Stop Description CPU[T/C]2_ITP/SRC[T/C]4 Output Enable 0 = Disable (Hi-Z Enable RESERVED, Set = 1 RESERVED, Set = 1 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]2_SATA Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z Enable RESERVED, Set = 1 CY28416 Description Description Page [+] Feedback ...
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... Allow control of SRC2_SATA with assertion of SW PCI_STP Free running Stopped with PCI_STP# Allow control of SRC[T/C]1 with assertion of SW PCI_STP Free running Stopped with PCI_STP# Allow control of SRC[T/C]1 with assertion of SW PCI_STP Free running Stopped with PCI_STP# RESERVED, Set = 0 CY28416 Page [+] Feedback ...
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... FS_C. Reflects the value of the FS_C pin sampled on power- FS_C was low during VTT_PWRGD# assertion FS_B. Reflects the value of the FS_B pin sampled on power- FS_B was low during VTT_PWRGD# assertion FS_A. Reflects the value of the FS_A pin sampled on power- FS_A was low during VTT_PWRGD# assertion CY28416 Page [+] Feedback ...
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... Crystal Recommendations The CY28416 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28416 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. ...
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... Figure example showing the relationship of clocks coming up. Unfortunately, we can not show all possible combinations, designers need to insure that from the first active clock output to the last takes no more than two full PCI clock cycles. CY28416 Page [+] Feedback ...
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... Figure 5. VTT_PWRGD# Timing Diagram Figure 5. VTT_PWRGD# Timing Diagram TT_P Low D elay >0. orm D_A = off O peration V TT_P toggle CY28416 Device is not affected, VTT_PW RGD# is ignored State Sam ple Inputs straps W ait for <1. nable O utputs ...
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... SDATA, SCLK Except internal pull-up resistors, 0 < Except internal pull-down resistors, 0 < – max load and freq per Table 6 and Figure 7 PD asserted, Outputs driven PD asserted, Outputs Tri-stated CY28416 Min. Max. Unit –0.5 4.6 V –0.5 4.6 V –0 0.5 VDC DD – ...
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... Measured at crossing point V OX Measured at crossing point Measured at crossing point V OX Measured at crossing point V OX Measured at crossing point V OX Measured from V = 0.175 0.525V OL OH Determined as a fraction of 2*(T – T )/( CY28416 Min. Max. Unit 47.5 52.5 % 69.841 71.0 ns – 10.0 ns – 500 ps – 300 ppm ...
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... Determined as a fraction of 2*(T – T )/( Math averages Figure 7 Math averages Figure 7 See Figure 7. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V CY28416 Min. Max. Unit – 125 ps 660 850 mv –150 – mv 220 550 mV – V ...
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... Ω Ω Figure 7. 0.7V Load Configuration Output under Test tDC 3. Package Type CY28416 Min. Max. Unit – 1000 ps – 1.8 ms 10.0 – – ns ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges system, provided that the system conforms to the I CY28416 51-85061-* Standard Specification ...
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... Document History Page Document Title: CY28416 Next Generation FTG for Intel Document #: 38-07657 Rev. *C REV. ECN NO. Issue Date ** 224420 See ECN RGL/TUJ New Data Sheet *A 318277 See ECN *B 375236 See ECN *C 385998 See ECN Document #: 38-07657 Rev. *C ® Architecture Orig. of Change ...