cy28359 Cypress Semiconductor Corporation., cy28359 Datasheet - Page 2

• Manufacturer Part Number: cy28359
• Description: 273-mhz 6-output Buffer For Ddr400 Dimms
• Manufacturer: Cypress Semiconductor Corporation.

Document #: 38-07636 Rev. **
Pin Description
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. The interface can also be
accessed during power down operation.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read,
Block Write and Block Read operation from any external I
Table 1. Command Code Definition
10
2
13,15,20
4,6,24
12,14,21
3,5,25
9
1
18
19
26
7,16,22,28
8,11,17,23,27
(6:5)
(4:0)
Bit
7
Pin
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
01
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be '00000'
BUF_INA,
BUF_INB
DDRA[0:2]C
DDRB[0:2]C
DDRA[0:2]T
DDRB[0:2]T
FB_OUTA
FB_OUTB
SCLK
SDATA
SEL_ADDR
VDD2.5
VSS
Name
VDD2.5
VDD2.5
VDD2.5
VDD2.5
VDD2.5
VDD2.5
PWR
PRELIMINARY
2
I/O
I/O
C
O
O
O
I
I
I
Description
controller. For Block Write/Read operation, the bytes must be
accessed in sequential order from lowest to highest byte (most
significant bit first) with the ability to stop after any complete
byte has been transferred. For Byte Write and Byte Read
operations, the system controller can access individual
indexed bytes. The offset of the indexed byte is encoded in the
command code, as described in Table 1.
The Block Write and Block Read protocol is outlined in Table 2
while Table 3 outlines the corresponding Byte Write and Byte
Read protocol.The slave receiver address is 11010010 (D2h)
or 11011100 (DCh) depending on state of ADDRSEL.
Reference input from chipset. 2.5V input.
Clock outputs. These outputs provide complementary
copies of BUF_INA & BUF_INB, respectively.
Clock outputs. These outputs provide copies of BUF_INA
& BUF_INB, respectively.
Feedback clock for chipset
SMBus clock input. Has pull-up resistor
SMBus data input. Has pull-up resistor
Address Select Pin. Has pull-down resistor
2.5V voltage supply
Ground
Description
CY28359
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