cy28349oxct SpectraLinear Inc, cy28349oxct Datasheet - Page 5

• Manufacturer Part Number: cy28349oxct
• Description: Ftg For Intel Pentium 4 Cpu And Chipsets
• Manufacturer: SpectraLinear Inc

Rev 1.0, November 24, 2006
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions such as individual
clock output buffers, etc. can be individually enabled or
disabled.
The register associated with the Serial Data Interface
initializes to its default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions.
Table 1. Command Code Definition
Table 2. Block Read and Block Write Protocol
11:18
20:27
29:36
38:45
Bit
2:8
10
19
28
37
46
...
...
...
...
1
9
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Byte Count – 8 bits
Acknowledge from slave
Data byte 0 – 8 bits
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data Byte N/Slave Acknowledge...
Data Byte N – 8 bits
Acknowledge from slave
Stop
6:0
Bit
7
Block Write Protocol
Description
0 = Block Read or Block Write operation
1 = Byte Read or Byte Write operation
Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations,
these bits should be ‘0000000’.
Data Protocol
The clock driver serial protocol accepts Byte Write, byte read,
Block Write and Block Read operation from the controller. For
Block Write/Read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For Byte Write and Byte Read operations,
the system controller can access individual indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The Block Write and Block Read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol.
The slave receiver address is 11010010 (D2h).
11:18
21:27
30:37
39:46
48:55
Bit
2:8
10
19
20
28
29
38
47
56
...
...
...
...
1
9
Descriptions
Start
Slave address – 7 bits
Write
Acknowledge from slave
Command Code – 8 bits
‘00000000’ stands for block operation
Acknowledge from slave
Repeat start
Slave address – 7 bits
Read
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data byte from slave – 8 bits
Acknowledge
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
Stop
Block Read Protocol
Description
CY28349
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