cy2267 Cypress Semiconductor Corporation., cy2267 Datasheet
cy2267
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cy2267 Summary of contents
Page 1
... Termination Techniques for Cypress Clock Generators” for more information on recommended system layout techniques. The CY2267 accepts a 14.318 MHz reference crystal or clock as its input and runs off a 3.3V supply. The CY2267 is available in a space-saving, low-cost 34-pin SSOP package and is pin-compatible with the CY2264 and CY2265. ...
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... USB clock output, 48 MHz IOCLK 31 I/O clock output, 24 MHz V 32 Voltage supply DD REFCLK 33 Reference clock output (14.318 MHz) for ISA slots (drives CPU clock select input, bit 2 (internal pull-up resistor to V Notes: 1. For best accuracy, use a parallel-resonant crystal, C Description = 17 pF. LOAD 2 CY2267 ) pF) LOAD ) DD ...
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... Supply Voltage ................................................. –0.5 to +7.0V Input Voltage ..............................................–0. Storage Temperature (Non-Condensing)... – +150 C Max. Soldering Temperature (10 sec)...................... +260 C Junction Temperature .............................................. +150 C Package Power Dissipation.............................................. 1W Static Discharge Voltage ........................................... >2000V (per MIL-STD-883, Method 3015) Description 3 CY2267 USBCLK IOCLK Hi-Z Hi-Z 48 MHz 24 MHz 48 MHz 24 MHz 48 MHz 24 MHz +0 ...
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... Three-state V = 3.6V Loaded Outputs CPU clocks = 66.67 MHz V = 3.6V Unloaded Outputs CY2267 Min. Max. Unit 2.0 0.8 CPUCLK 2.4 PCICLK USBCLK IOCLK REFCLK CPUCLK 0.4 PCICLK USBCLK IOCLK REFCLK 10 100 –10 +10 180 120 ...
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... Measured between 0.8V and 2.0V Measured between 2.0V and 0.8V Measured between 2.0V and 0.8V Measured at 1.5V Measured at 1.5V CPU Clock jitter USB Clock, I/O Clock, and PCI Clock jitter CPU clock stabilization from power-up PCI clock stabilization from power-up 1.5V 2267–c 5 CY2267 Min. Typ. Max. Unit 5.0 ns 12 ...
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... Switching Waveforms (continued) CPUCLK Outputs HIGH/LOW Time t 1C 2.4V 2.4V OUTPUT All Outputs Rise/Fall Time 2.0V 2.0V OUTPUT 0. Clock Skew 1.5V CPUCLK–CPUCLK 1. CPU-PCI Clock Skew CPUCLK 1.5V 1.5V PCICLK t 6 3.3V 0.4V 0.4V 0V 2267– 3.3V 0. 2267–e 2267–f 2267–g 6 CY2267 ...
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... If a Ferrite Bead is used F– tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. is the loaded characteristic impedance trace from the clock generator V island. Ensure that the Ferrite Bead offers CY2267 of LOAD is the series terminating series ...
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... Test Circuit 0 0.1 F 0.1 F Note: All capacitors should be placed as close to each pin as possible. Ordering Information Package Ordering Code Name CY2267PVC–1 O34 34-Pin SSOP Document #: 38–00534– 0 OUTPUTS C LOAD Operating Package Type Range Commercial 8 CY2267 0.1 F ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 34-Pin Shrunk Small Outline Package O34 CY2267 ...