gt3200 SMC Corporation, gt3200 Datasheet - Page 11

• Manufacturer Part Number: gt3200
• Description: Usb2.0 Phy Ic
• Manufacturer: SMC Corporation

USB2.0 PHY IC
SMSC GT3200, SMSC USB3250
DATA[15:0]
TXVALID
TXREADY
VALIDH
RXVALID
RXACTIVE
RXERROR
NAME
DIRECTION
Output
Output
Output
Output
Input
Bidir
Bidir
ACTIVE
LEVEL
High
High
High
High
High
N/A
N/A
Table 4.2 Data Interface Signals
Transmit Valid. Indicates that the TXDATA bus is valid for
transmit. The assertion of TXVALID initiates the transmission of
SYNC on the USB bus. The negation of TXVALID initiates EOP
on the USB.
Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT)
must not be changed on the de-assertion or assertion of TXVALID.
The PHY must be in a quiescent state when these inputs are
changed.
Transmit Data Ready. If TXVALID is asserted, the SIE must
always have data available for clocking into the TX Holding
Register on the rising edge of CLKOUT. TXREADY is an
acknowledgement to the SIE that the transceiver has clocked the
data from the bus and is ready for the next transfer on the bus. If
TXVALID is negated, TXREADY can be ignored by the SIE.
Transmit/Receive High Data Bit Valid (used in 16-bit mode
only). When TXVALID = 1, the 16-bit data bus direction is
changed to inputs. If VALIDH is asserted, DATA[15:0] is valid for
transmission. If deasserted, only DATA[7:0] is valid for
transmission. The DATA bus is driven by the SIE.
When TXVALID = 0 and RXVALID = 1, the 16-bit data bus
direction is changed to outputs. If VALIDH is asserted, the
DATA[15:0] outputs are valid for receive. If deasseted, only
DATA[7:0] is valid for receive. The DATA bus is read by the SIE.
Receive Data Valid. Indicates that the RXDATA bus has received
valid data. The Receive Data Holding Register is full and ready to
be unloaded. The SIE is expected to latch the RXDATA bus on the
rising edge of CLKOUT.
Receive Active. Indicates that the receive state machine has
detected Start of Packet and is active.
Receive Error. 0: Indicates no error. 1: Indicates a receive error
has been detected. This output is clocked with the same timing as
the RXDATA lines and can occur at anytime during a transfer.
DATASHEET
TXVALID
TXVALID
0
0
0
1
1
0
0
1
6
DATA BUS. 8-BIT UNIDIRECTIONAL MODE.
DATA BUS. 16-BIT BIDIRECTIONAL MODE.
RXVALID
RXVALID
X
X
X
0
1
1
0
1
DESCRIPTION
DATA[15:0]
Not used
DATA[15:8] output is valid for receive
DATA[7:0] input is valid for transmit
VALIDH
X
0
1
0
1
DATA[15:0]
Not used
DATA[7:0] output is valid
for receive
DATA[15:0] output is
valid for receive
DATA[7:0] input is valid
for transmit
DATA[15:0] input is valid
for transmit
Revision 1.3 (10-05-04)