ds2065w Maxim Integrated Products, Inc., ds2065w Datasheet - Page 10

• Manufacturer Part Number: ds2065w
• Description: 3.3v Single-piece 8mb Nonvolatile Sram Integrated Products
• Manufacturer: Maxim Integrated Products, Inc.

DS2065W 3.3V Single-Piece 8Mb
Nonvolatile SRAM
The DS2065W executes a read cycle whenever WE (write
enable) is inactive (high) and CE (chip enable) is active
(low). The unique address specified by the 20 address
inputs (A0 to A19) defines which of the 1,048,576 bytes of
data is to be accessed. Valid data will be available to the
eight data output drivers within t
the last address input signal is stable, providing that CE
and OE (output enable) access times are also satisfied. If
CE and OE access times are not satisfied, then data
access must be measured from the later-occurring signal
(CE or OE) and the limiting parameter is either t
or t
The DS2065W executes a write cycle whenever the CE
and WE signals are active (low) after address inputs
are stable. The later-occurring falling edge of CE or WE
will determine the start of the write cycle. The write
cycle is terminated by the earlier rising edge of CE or
WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (t
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However, if the output drivers have been enabled (CE
and OE active) then WE will disable the outputs in t
from its falling edge.
The DS2065W provides full functional capability for V
greater than 3.0V and write-protects by 2.8V. Data is
maintained in the absence of V
support circuitry. The NV static RAM constantly moni-
tors V
SRAM automatically write-protects itself. All inputs
become “don’t care”, and all data outputs become high
impedance. As V
(V
Memory Operation Truth Table
X = Don’t care.
10
SW
OE
), the power-switching circuit connects the lithium
____________________________________________________________________
WE
for OE, rather than address access.
CC
1
1
0
X
. Should the supply voltage decay, the NV
CC
CE
0
0
0
1
falls below approximately 2.5V
WR
Data-Retention Mode
) before another cycle can
ACC
CC
OE
0
1
X
X
(access time) after
without additional
Write Mode
Read Mode
CO
for CE
ODW
CC
Standby
MODE
Read
Read
Write
energy source to the RAM to retain data. During power-
up, when V
circuit connects external V
nects the lithium energy source. Normal RAM operation
can resume after V
duration of t
When V
charges the battery. The UL-approved charger circuit
includes short-circuit protection and a temperature-sta-
bilized voltage reference for on-demand charging of
the internal battery. Typical data-retention expectations
of 3 years
A maximum of 96 hours of charging time is required to
fully charge a depleted battery.
When the external V
out-of-tolerance trip point, the output RST is forced
active (low). Once active, the RST is held active until
the V
tery. On power-up, the RST output is held active until
the external supply is greater than the selected trip
point and one reset timeout period (t
This is sufficiently longer than t
SRAM is ready for access by the microprocessor.
The DS2065W is shipped from Dallas Semiconductor
with the lithium battery electrically disconnected, guar-
anteeing that no battery capacity has been consumed
during transit or storage. As shipped, the lithium battery
is ~60% charged, and no preassembly charging oper-
ations should be attempted.
When V
the lithium battery is enabled for backup operation. A
96 hour initial battery charge time is recommended for
new system installations.
CC
CC
CC
supply has fallen below that of the internal bat-
per charge cycle are achievable.
is first applied at a level greater than V
REC
CC
is greater than V
rises above V
.
Standby
Active
Active
Active
Freshness Seal and Shipping
I
CC
CC
CC
System Power Monitoring
supply falls below the selected
exceeds V
CC
TP
SW
to the RAM and discon-
REC
, an internal regulator
, the power-switching
Battery Charging
TP
High Impedance
High Impedance
High Impedance
RPU
to ensure that the
OUTPUTS
for a minimum
) has elapsed.
Active
TP
,