ds265188-port-t1-e1-j1-transc Maxim Integrated Products, Inc., ds265188-port-t1-e1-j1-transc Datasheet - Page 259

• Manufacturer Part Number: ds265188-port-t1-e1-j1-transc
• Description: Ds26518 8-port T1/e1/j1 Transceiver
• Manufacturer: Maxim Integrated Products, Inc.

10.6.1 Extended BERT Register Definitions
Table 10-28. Extended BERT Register Set
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 1: 55 Octet Pattern (55OCT). This bit selects data pattern used by the transmit and receive circuits.
Bit 0: Byte Alignment to DS0 Boundary (BALIGN). A low-to-high transition causes the transmit BERT pattern to
be byte-aligned to the DS0 boundary. This bit should be toggled from low to high when a pattern load is executed
(BC1.TC).
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 3: BERT Receive All-Ones Condition (BRA1). This bit is set when 32 consecutive ones are received and
clears when at least one “zero” is received.
Bit 2: BERT Receive All-Zeros Condition (BRA0). This bit is set when 32 consecutive zeros are received and
clears when at least one “one” is received.
Bit 1: BERT Receive Loss of Synchronization Condition (BRLOS). This bit is set whenever the receive BERT
begins searching for a pattern and clears when BERT enters SYNC condition.
Bit 0: BERT in Synchronization Condition (BSYNC). This bit is set when the incoming pattern matches for 32
consecutive bit positions and remains set until the BERT enters loss of synchronization condition.
ADDRESS
1400h
1401h
1402h
1403h
1404h
1405h
0 = 55 Octet pattern disabled.
1 = 55 Octet pattern enabled, when modified 55 Octet (Daly) pattern is selected by BC1.PSn register bits.
—
—
7
0
7
0
BLSR1
BLSR2
NAME
BSIM1
BSIM2
BRSR
BC3
BC3
BERT Control Register 3
1400h + (10h x (n - 1)) : where n = 1 to 8
BRSR
BERT Real-Time Status Register
1401h + (10h x (n - 1)) : where n = 1 to 8
—
—
6
0
6
0
BERT Control Register 3
BERT Real-Time Status Register
BERT Latched Status Register 1
BERT Status Interrupt Mask Register 1
BERT Latched Status Register 2
BERT Status Interrupt Mask Register 2
—
—
5
0
5
0
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—
—
4
0
4
0
DESCRIPTION
BRA1
—
3
0
3
0
DS26518 8-Port T1/E1/J1 Transceiver
BRA0
—
2
0
2
0
BRLOS
55OCT
1
0
1
0
BALIGN
BSYNC
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
R