ds21372 Maxim Integrated Products, Inc., ds21372 Datasheet - Page 8

• Manufacturer Part Number: ds21372
• Description: Ds21372 3.3v Bit Error Rate Tester Bert
• Manufacturer: Maxim Integrated Products, Inc.

PCR: PATTERN CONTROL REGISTER (ADDRESS=06 HEX)
(MSB)
SYMBOL
RESYNC
TL
SYNCE
QRSS
LPBK
LC
RL
TL
PS
QRSS
POSITION
PCR.7
PCR.6
PCR.5
PCR.4
PCR.3
PCR.2
PCR.1
PCR.0
PS
NAME AND DESCRIPTION
Transmit Load. A low to high transition loads the pattern
generator with the contents of the Pattern Set Registers. PCR.7 is
logically ORed with the input pin TL. Must be cleared and set
again for subsequent loads.
Zero Suppression Select. Forces a 1 into the pattern whenever
the next 14 bit positions are all 0s. Should only be set when
using the QRSS pattern.
0 = Zero suppression disabled
1 = Zero suppression enabled
Pattern Select.
0 = Repetitive Pattern
1 = Pseudorandom Pattern
Latch Count Registers. A low to high transition latches the bit
and error counts into the user accessible registers BCR and
BECR and clears the internal register count. PCR.4 is logically
OR’ed with input pin LC. Must be cleared and set again for
subsequent loads.
Receive Data Load. A transition from low to high loads the
previous 32 bits of data received at RDATA into the Pattern
Receive Registers (PRR). PCR.3 is logically OR’ed with input
pin RL. Must be cleared and set again for subsequent latches.
SYNC Enable.
0 = auto resync is enabled.
1 = auto resync is disabled.
Initiate Manual Resync Process. A low to high transition will
force the DS21372 to resynchronize to the incoming pattern at
RDATA. Must be cleared and set again for a subsequent resync.
Transmit/Receive Loopback Select. When enabled, the
RDATA input is disabled; TDATA continues to output data as
normal. See Figure 1.
0 = loopback disabled
1 = loopback enabled
LC
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RL
SYNCE
RESYNC
LPBK
(LSB)
DS21372