ds2156gn Maxim Integrated Products, Inc., ds2156gn Datasheet - Page 223
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ds2156gn
Manufacturer Part Number
ds2156gn
Description
Ds2156, Ds2156l, Ds2156ln T1/e1/j1 Single-chip Transceiver Tdm/utopia Ii Interface
Manufacturer
Maxim Integrated Products, Inc.
Datasheet
1.DS2156GN.pdf
(265 pages)
- Current page: 223 of 265
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31.2 UTOPIA Backplane Mode
ATM traffic can be assigned on a fractional basis. See Section 24 for UTOPIA operation.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 0/Receive Gapped-Clock Enable (RGPCKEN)
Bit 1/Receive Channel-Data Format (RDATFMT)
Bit 2/Transmit Gapped-Clock Enable (TGPCKEN)
Bit 3/Transmit Channel-Data Format (TDATFMT)
Bit 4/Connect RCLK to Receive UTOPIA Interface (CRRUI). This bit selects either a constant clock (RCLK)
or a gapped clock from the framer (programmed by the user) as its data clock.
Bit 5/Connect TCLK to Transmit UTOPIA Interface (CTTUI). This bit selects either a constant clock (TCLK)
or a gapped clock from the framer (programmed by the user) as its data clock.
Bit 6/Interrupt Disable (INTDIS). This bit is convenient for disabling interrupts without altering the various
interrupt mask register settings.
Bit 7/Transmit Multiframe Sync Source (TMSS). Should be set = 0 only when transmit hardware signaling is
enabled.
0 = RCHCLK functions normally
1 = enable gapped bit-clock output on RCHCLK
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in seven out of the 8 bits)
0 = TCHCLK functions normally
1 = enable gapped bit-clock output on TCHCLK
0 = 64kbps (data contained in all 8 bits)
1 = 56kbps (data contained in seven out of the 8 bits)
0 = gated clock is connected to receive UTOPIA interface
1 = RCLK is connected to receive UTOPIA interface
0 = gated clock is connected to transmit UTOPIA interface
1 = TCLK is connected to transmit UTOPIA interface
0 = interrupts are enabled according to the various mask register settings
1 = interrupts are disabled regardless of the mask register settings
0 = elastic store is source of multiframe sync
1 = framer or TSYNC pin is source of multiframe sync
TMSS
7
0
INTDIS
6
0
CCR3
Common Control Register 3
72h
CTTUI
5
0
CRRUI
4
0
223 of 265
TDATFMT
3
0
TGPCKEN
2
0
RDATFMT
1
0
RGPCKEN
0
0
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