ds1501wst-r Maxim Integrated Products, Inc., ds1501wst-r Datasheet
ds1501wst-r
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ds1501wst-r Summary of contents
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GENERAL DESCRIPTION The DS1501/DS1511 are full-function, year 2000- compliant real-time clock/calendars (RTCs) with an RTC alarm, watchdog timer, power-on reset, battery monitors, 256 bytes NV SRAM, and a 32.768kHz output. User access to all registers within the DS1501/DS1511 is ...
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ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground……………………………………………………..……....-0.5V to +6.0V Operating Temperature Range (EDIP Module).…………………………………………………..………....0°C to +70°C Operating Temperature Range, DS1501 Operating Temperature Range, DS1511……………………………………………………………….……..0°C to +70°C Storage Temperature Range, DS1501 Storage Temperature Range, DS1511………………………………………………………………….…..-40°C to +70°C ...
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DC ELECTRICAL CHARACTERISTICS ( 0°C to +70° PARAMETER Battery Current, BB32 = 0, EOSC = 0 Battery Current, BB32 = 0, EOSC = 1 V Current BB32 = 1, SQW Open BAUX CRYSTAL ...
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AC OPERATING CHARACTERISTICS (V = 3.3V ±10 0°C to +70° PARAMETER Read Cycle Time Address Access Time Low-Z CE Access Time CE Data Off Time Low-Z (0°C to +85°C) ...
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Figure 2. Write Cycle Timing, Write-Enable Controlled A0– DQ0–DQ7 Figure 3. Write Cycle Timing, Chip-Enable Controlled A0- DQ0-DQ7 t WC VALID WEW WEZ DATA OUTPUT DATA INPUT ...
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Figure 4. Burst Mode Timing Waveform A 0 – – POWER-UP/DOWN CHARACTERISTICS PARAMETER Before Power-Fail IH V ...
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Figure 5. 3.3V Power-Up/Down Waveform Timing Figure 6. 5V Power-Up/Down Waveform Timing Warning: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode ...
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WAKEUP/KICKSTART TIMING (T = +25°C) (Figure 7) A PARAMETER Kickstart-Input Pulse Width Wakeup/Kickstart Power-On Timeout Note: Time intervals shown above are referenced in Wakeup/Kickstart. Figure 7. Wakeup/Kickstart Timing Diagram ...
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PIN DESCRIPTION PIN DIP, SO EDIP TSOP — 6–10 6–10 13–17 11–13, 11–13, 18–20, DQ0–DQ7 15–19 15–19 22– ...
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Figure 8. Block Diagram X1 32.768kHz CLOCK OSCILLATOR X2 V BAT V BAT POWER CONTROL V BAUX WRITE PROTECTION, AND POWER-ON GND RESET KS Figure 9. Typical Crystal Layout LOCAL GROUND PLANE (LAYER 2) CRYSTAL CLOCK ALARM AND WATCHDOG COUNTDOWN ...
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DETAILED DESCRIPTION The RTC registers are double buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user ...
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DATA RETENTION MODE The DS1501/DS1511 are fully accessible, and data can be written and read only when V However, when V falls below the power-fail point V CC registers and SRAM are blocked from any access. While in the data ...
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The third method of reading the time and date uses the alarm function. The alarm can be configured to activate once per second, and the time-of-day alarm-interrupt enable bit (TIE) is enabled. The TE bit should always be enabled. When ...
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USING THE CLOCK ALARM The alarm settings and control reside within registers 08h to 0Bh (Table 2). The TIE bit and alarm mask bits AM1 to AM4 must be set as described below for the IRQ or PWR outputs to ...
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Control A Register (0Eh) Bit 7 Bit 6 BLF1 BLF2 BLF1, Valid RAM and Time Bit 1 (0Eh Bit 7); BLF2, Valid RAM and Time Bit 2 (0Eh Bit 6) These status bits give the condition of any batteries attached ...
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Control B Register (0Fh) Bit 7 Bit TE, Transfer Enable Bit (0Fh Bit 7) When the TE bit is 1, the update transfer functions normally by advancing the counts once per second. When the TE bit is ...
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BAT regardless of the state of the watchdog enable (WDE) bit, to serve as an indication to the processor that a watchdog timeout has occurred. The watchdog timer operates ...
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The interrupt flag bit (either TDF or KSF) associated with the attempted power-on sequence remains set until cleared by software during a subsequent system power-on applied within the timeout period, the system power-on sequence continues, as shown ...
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ORDERING INFORMATION (continued) PART VOLTAGE (V) DS1501WN 3.3 DS1501WN+ 3.3 DS1501WS 3.3 DS1501WS+ 3.3 DS1501WSN 3.3 DS1501WSN+ 3.3 DS1501WSN/T&R 3.3 DS1501WSN+T&R 3.3 DS1501WS/T&R 3.3 DS1501WS+T&R 3.3 DS1501Y 5.0 DS1501Y+ 5.0 DS1501YE 5.0 DS1501YE+ 5.0 DS1501YEN 5.0 DS1501YEN+ 5.0 DS1501YEN/T&R 5.0 ...
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PIN CONFIGURATIONS TOP VIEW PWR RST 4 25 Dallas IRQ 5 24 Semiconductor DS1501 DQ0 11 18 ...
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