ds1236as-5t-r Maxim Integrated Products, Inc., ds1236as-5t-r Datasheet - Page 3

• Manufacturer Part Number: ds1236as-5t-r
• Description: Ds1236a Micromanager Chip
• Manufacturer: Maxim Integrated Products, Inc.

POWER MONITOR
The DS1236A employs a band gap voltage reference and a precision comparator to monitor the 5-volt
supply (V
RST and
5% operation option (DS1236A-5) is set for 4.75 volts (4.62 typical). The RST and
excellent for microprocessor reset control, as processing is stopped at the last possible moment of in-
tolerance V
typical) after V
operation described above is obtained with the reset control pin (RC) connected to GND (NMOS mode).
Please review the reset control section for more information.
WATCHDOG TIMER
The DS1236A provides a watchdog timer function which forces the RST and
state when the strobe input (
ms typically with a maximum timeout of 600 ms. The watchdog timeout period begins as soon as RST
and
timer is reset and begins to time out again. The
watchdog timer does not time out, a high-to-low transition on
(minimum timeout) from a reset. If the watchdog timer is allowed to time out, the RST and
are driven to the active state for 25 ms minimum. The
address, data, and/or control signals. Under normal operating conditions, these signals would routinely
reset the watchdog timer prior to timeout. If the watchdog timer is not required, two methods have been
provided to disable it.
Permanently grounding the IN pin in the CMOS mode (RC=1) will disable the watchdog. In normal
operation with RC=1, the watchdog is disabled as soon as the IN pin is below V
falling edge on
power is between V
watchdog timer is not affected by the IN pin when in NMOS mode (RC=0).
If the
the
falls to V
PUSHBUTTON RESET
An input pin is provided on the DS1236A for direct connection to a pushbutton. The pushbutton reset
input requires an active low signal. Internally, this input is pulled high by a 10k resistor whenever V
greater than V
driven to the active state for 25 ms minimum. This 25 ms delay begins as the pushbutton is released from
a low level. A typical example of the power monitor, watchdog timer, and pushbutton reset connections
are shown in NO TAG. The
and the reset control (RC) is tied high (CMOS mode). The
below V
RST
NMI
ST
RST
outputs are driven to the active state. The V
output will occur only at power-up, or when the
NMI
input open. Independent of the state of the RC pin, the watchdog is also disabled as soon as V
BAT
CCTP
CC
are inactive. If a high-to-low transition occurs at the
RST
CC
. Timing of the
signal is required to monitor supply voltages, the watchdog may also be disabled by leaving
) in microprocessor-based systems. When an out-of-tolerance condition occurs, the RST and
.
. On power-up, the RST and
BAT
outputs will become active as V
CCTP
ST
. The
will generate an
TP
is reached to allow the power supply and microprocessor to stabilize. Note: The
and V
PBRST
PBRST
ST
PBRST
CCTP
) is not stimulated for a predetermined time period. This time period is 400
pin is also debounced and timed such that the RST and
-generated RST is illustrated in Figure 1.
, as an
NMI
input is disabled whenever the IN pin voltage level is less than V
when IN is below V
NMI
RST
CC
signals are held active for a minimum of 25 ms (100 ms
ST
will be returned immediately after the
3 of 20
CC
falls below 4.5 volts (4.37 typical). The V
trip point (V
input timing is shown in NO TAG. To guarantee the
ST
ST
PBRST
pin is strobed. As shown in the NO TAG, a
input can be derived from microprocessor
TP
. This allows the processor to verify that
CCTP
ST
ST
input is also disabled whenever V
input prior to timeout, the watchdog
) is set for 10% operation so that the
must occur at or less than 100 ms
RST
TP
. With IN grounded, an
signals to the active
RST
RST
ST
RST
CCTP
strobe. The
outputs are
signals are
DS1236A
outputs
for the
CC
CC
CC
TP
is
is