ds1086lut Maxim Integrated Products, Inc., ds1086lut Datasheet - Page 14

• Manufacturer Part Number: ds1086lut
• Description: Ds1086l 3.3v Spread-spectrum Econoscillator
• Manufacturer: Maxim Integrated Products, Inc.

3.3V Spread-Spectrum EconOscillator
Figure 5. Slave Address
Figure 6. 2-Wire AC Characteristics
The DS1086L communicates through a 2-wire serial
interface. A device that sends data onto the bus is
defined as a transmitter, and a device receiving data
as a receiver. The device that controls the message is
called a “master.” The devices that are controlled by
the master are “slaves.” A master device that generates
the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions must con-
trol the bus. The DS1086L operates as a slave on the 2-
wire bus. Connections to the bus are made through the
open-drain I/O lines SDA and SCL.
The following bus protocol has been defined (see
Figures 4 and 6):
•
•
14
_______2-Wire Serial Port Operation
SDA
SCL
______________________________________________________________________________________
Data transfer can be initiated only when the bus is
not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
MSB
STOP
1
t
IDENTIFIER
BUF
DEVICE
0
START
1
t
HD:STA
2-Wire Serial Data Bus
t
LOW
1
A2
ADDRESS
DEVICE
A1
t
R
t
HD:DAT
A0
t
F
t
HIGH
R/W
LSB
t
SU:DAT
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain HIGH.
Start data transfer: A change in the state of the data
line, from HIGH to LOW, while the clock is HIGH,
defines a START condition.
Stop data transfer: A change in the state of the data
line, from LOW to HIGH, while the clock line is HIGH,
defines the STOP condition.
Data valid: The state of the data line represents valid
data when, after a START condition, the data line is sta-
ble for the duration of the HIGH period of the clock sig-
nal. The data on the line must be changed during the
LOW period of the clock signal. There is one clock
pulse per bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between START and STOP con-
REPEATED
in the data line while the clock line is HIGH are
interpreted as control signals.
START
t
SU:STA
t
HD:STA
t
SP
t
SU:STO