74AHC574D,118 NXP Semiconductors, 74AHC574D,118 Datasheet - Page 4

• Manufacturer Part Number: 74AHC574D,118
• Description: IC OCT D F-F POS-EDG TRIG 20SOIC
• Manufacturer: NXP Semiconductors
• Series: 74AHCr
• Type: D-Type Busr

Specifications of 74AHC574D,118

• Package / Case: 20-SOIC (7.5mm Width)
• Function: Standard
• Output Type: Tri-State Non Inverted
• Number Of Elements: 1
• Number Of Bits Per Element: 8
• Frequency - Clock: 75MHz
• Delay Time - Propagation: 9ns
• Trigger Type: Positive Edge
• Current - Output High, Low: 8mA, 8mA
• Voltage - Supply: 2 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 1
• Logic Family: AHC
• Logic Type: D-Type Edge Triggered Flip-Flop
• Polarity: Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 4.4 ns at 5 V
• High Level Output Current: - 8 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 2 V
• Dc: 0728
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74AHC574D-T; 74AHC574D-T; 935263080118

NXP Semiconductors
5. Pinning information
Table 2.
74AHC_AHCT574_2
Product data sheet
Symbol
OE
D[0:7]
GND
CP
Q[0:7]
V
Fig 5.
CC
Pin configuration SO20, TSSOP20
Pin description
GND
OE
Pin
1
2, 3, 4, 5, 6, 7, 8, 9
10
11
19, 18, 17, 16, 15, 14, 13, 12 3-state flip-flop output
20
D0
D1
D2
D3
D4
D5
D6
D7
10
1
2
3
4
5
6
7
8
9
5.1 Pinning
5.2 Pin description
74AHCT574
74AHC574
001aah037
20
19
18
17
16
15
14
13
12
11
Description
3-state output enable input (active LOW)
data input
ground (0 V)
clock input (LOW-to-HIGH, edge triggered)
supply voltage
V
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP
CC
Rev. 02 — 24 January 2008
Octal D-type flip-flop; positive edge-trigger; 3-state
Fig 6.
74AHC574; 74AHCT574
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as a
supply pin or input.
Pin configuration DHVQFN20
index area
terminal 1
D0
D1
D2
D3
D4
D5
D6
D7
Transparent top view
2
3
4
5
6
7
8
9
74AHCT574
74AHC574
GND
(1)
19
18
17
16
15
14
13
12
001aah666
© NXP B.V. 2008. All rights reserved.
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
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