st2064b Sitronix Technology Corporation, st2064b Datasheet - Page 9

• Manufacturer Part Number: st2064b
• Description: 8 Bit Microcontroller With 64k Bytes Rom
• Manufacturer: Sitronix Technology Corporation

9
9.1 Interrupt description
Brk
Instruction ‘ BRK’ will cause software interrupt when interrupt
disable flag (I) is cleared. Hardware will push ‘ PC’ ,
Register to stack and set interrupt disable flag (I). Program
counter then will be loaded with the BRK vector from locations
$7FFE and $7FFF.
Reset
A positive transition of RESET pin will then cause an
initialization sequence to begin. After the system has been
operating, a low on this line at least of two clock cycles will
cease ST2064B activity. When a positive edge is detected,
there is an initialization sequence lasting six clock cycles. Then
the interrupt mask flag is set, the decimal mode is cleared and
the program counter will loaded with the restart vector from
locations $7FFC (low byte) and $7FFD (high byte). This is the
start location for program control. This input should be high in
normal operation.
INTX Interrupt
The IRX (INTX interrupt request) flag will be set while INTX
edge signal occurs. The INTX interrupt will be active once IEX
(INTX interrupt enable) is set, and interrupt mask flag is
cleared. Hardware will push ‘ PC’ , ‘ P ’ Register to stack and set
interrupt mask flag (I). Program counter will be loaded with the
INTX vector from locations $7FF8 and $7FF9.
DAC Interrupt
The IRDAC (DAC interrupt request) flag will be set while reload
signal of DAC occurs. Then the DAC interrupt will be executed
when IEDAC (DAC interrupt enable) is set, and interrupt mask
flag is cleared. Hardware will push ‘ PC’ , ‘ P ’ Register to stack
and set interrupt mask flag (I). Program counter will be loaded
with the DAC vector from locations $7FF6 and $7FF7.
Ver. 3.0
9
.
.
I
I
N
N
T
T
E
E
RESET
Name
INTX
DAC
BRK
R
R
PT
BT
T0
T1
-
R
R
U
U
P
P
T
T
INT/EXT
INT/EXT
S
External
External
External
S
Internal
Internal
Internal
Signal
-
Vector address
$7FFD,$7FFC
$7FFB,$7FFA
$7FEF,$7FEE
$7FFF,$7FFE
$7FF9,$7FF8
$7FF7,$7FF6
$7FF5,$7FF4
$7FF3,$7FF2
$7FF1,$7FF0
TABLE 9-1 Interrupt Vectors
‘ P ’
9/57
T0 Interrupt
The IRT0 (TIMER0 interrupt request) flag will be set while T0
overflows. With IET0 (TIMER0 interrupt enable) being set, the
T0 interrupt will execute, and interrupt mask flag will be cleared.
Hardware will push ‘ PC’ ,
interrupt mask flag (I). Program counter will be loaded with the
T0 vector from locations $7FF4 and $7FF5.
T1 Interrupt
The IRT1 (TIMER1 interrupt request) flag will be set while T1
overflows. With IET1 (TIMER1 interrupt enable) being set, the
T1 interrupt will execute, and interrupt mask flag will be cleared.
Hardware will push ‘ PC’ ,
interrupt mask flag (I). Program counter will be loaded with the
T1 vector from locations $7FF2 and $7FF3.
PT Interrupt
The IRPT (Port-A interrupt request) flag will be set while Port-A
transition signal occurs. With IEPT (PT interrupt enable) being
set, the PT interrupt will be execute, and interrupt mask flag will
be cleared. Hardware will push ‘ PC’ , ‘ P ’ Register to stack and
set interrupt mask flag (I). Program counter will be loaded with
the PT vector from locations $7FF0 and $7FF1.
BT Interrupt
The IRBT (Base timer interrupt request) flag will be set when
Base Timer overflows. The BT interrupt will be executed once
the IEBT (BT interrupt enable) is set and the interrupt mask flag
is cleared. Hardware will push ‘ PC’ , ‘ P ’ Register to stack and
set interrupt mask flag (I). Program counter will be loaded with
the BT vector from locations $7FEE and $7FEF.
All interrupt vectors are listed in TABLE 9-1.
Priority
4
5
7
8
1
2
3
6
-
Reset vector
PA0 edge interrupt
Reload DAC data interrupt
Timer0 interrupt
Timer1 interrupt
Port-A transition interrupt
Base Timer interrupt
Software BRK operation vector
Reserved
Comment
‘ P ’ Register to stack and set
‘ P ’ Register to stack and set
ST2064B
5/8/09