sm59d04g2 SyncMOS Technologies,Inc, sm59d04g2 Datasheet - Page 30

• Manufacturer Part Number: sm59d04g2
• Description: 8-bits Micro-controller 16kb+ Isp Flash & 1kb Ram Embedded
• Manufacturer: SyncMOS Technologies,Inc

Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M031
CP/ RL2 : Capture/Reload select. CP/ RL2 = 1 causes captures to occur on negative
Mnemonic: T2CON
EXEN2: Timer 2 external enable. When set, allows a capture or reload to occur as
TF2
DCEN: When set, this bit allows Timer 2 to be configured as an up/down counter.
RCLK: Receive clock enable. When set, causes the serial port to use Timer 2
T2OE: Timer 2 Output Enable bit.
Mnemonic: T2MOD
TCLK: Transmit clock enable. When set, causes the serial port to use Timer 2
7
EXF2: Timer 2 external flag is set when either a capture or reload is caused by a
C/ T2 : Timer or counter select for Timer 2. C/ T2 = 0 for timer function. C/ T2 = 1
TR2: Start/Stop control for Timer 2. TR2 = 1 starts the timer.
TF2: Timer 2 overflow flag is set by a Timer 2 overflow and must be cleared by
7
-
EXF2
software. TF2 will not be set when either RCLK = 1 or TCLK = 1.
negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is
enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt
routine. EXF2 must be cleared by software. EXF2 does not cause an
interrupt in up/down counter mode (DCEN = 1).
overflow pluses for its receive clock in serial port Modes 1 and 3. RCLK =
0 causes Timer 1 overflows to be used for the receive clock.
overflow pulses for it’s transmit clock in serial port Modes 1 and 3. TCLK =
0 causes Timer 1 overflows to be used for the transmit clock.
a result of a negative transition on T2EX if Timer 2 is not being used to
clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
for external event counter (falling edge triggered).
transitions at T2EX if EXEN2 = 1. CP/ RL2 = 0 causes automatic reloads
to occur when Timer 2 overflows or negative transitions occur at T2EX
when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and
the timer is forced to auto-reload on Timer 2 overflow.
6
6
-
RCLK
5
5
-
TCLK
4
4
-
EXEN2
3
3
-
30
TR2
2
2
-
C/
16KB+ ISP Flash & 1KB RAM embedded
T2OE
1
T2
1
Address: C9h
CP/
DCEN
Ver.C SM59D04G2 07/2009
Address: C8h
0
0
RL2
8-Bits Micro-controller
Reset
x0h
Reset
SM59D04G2
00h