sm59d04g2 SyncMOS Technologies,Inc, sm59d04g2 Datasheet - Page 56

• Manufacturer Part Number: sm59d04g2
• Description: 8-bits Micro-controller 16kb+ Isp Flash & 1kb Ram Embedded
• Manufacturer: SyncMOS Technologies,Inc

12.1.3
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M031
KBF7: EEI line 7 flag
KBF6: EEI line 6 flag
KBF5: EEI line 5 flag
KBF4: EEI line 4 flag
KBF3: EEI line 3 flag
KBF2: EEI line 2 flag
KBF1: EEI line 1 flag
KBF0: EEI line 0 flag
Mnemonic: KBF
KBF7
EEI flag register
R
Set by hardware when the port line 7 detects a programmed level. It generates a EEI
interrupt request if the KBE.7 bit in KBE register is set.
This register is read only access; the flag is automatically cleared by reading the register.
Set by hardware when the port line 6 detects a programmed level. It generates a EEI
interrupt request if the KBE.6 bit in KBE register is set.
This register is read only access; the flag is automatically cleared by reading the register.
Set by hardware when the port line 5 detects a programmed level. It generates a EEI
interrupt request if the KBE.5 bit in KBE register is set.
This register is read only access; the flag is automatically cleared by reading the register.
Set by hardware when the port line 4 detects a programmed level. It generates a EEI
interrupt request if the KBE.4 bit in KBE register is set.
This register is read only access; the flag is automatically cleared by reading the register.
Set by hardware when the port line 3 detects a programmed level. It generates a EEI
interrupt request if the KBE.3 bit in KBE register is set.
This register is read only access; the flag is automatically cleared by reading the register.
Set by hardware when the port line 2 detects a programmed level. It generates a EEI
interrupt request if the KBE.2 bit in KBE register is set.
This register is read only access; the flag is automatically cleared by reading the register.
Set by hardware when the port line 1 detects a programmed level. It generates a EEI
interrupt request if the KBE.1 bit in KBE register is set.
This register is read only access; the flag is automatically cleared by reading the register.
Set by hardware when the port line 0 detects a programmed level. It generates a EEI
interrupt request if the KBE.0 bit in KBE register is set.
This register is read only access; the flag is automatically cleared by reading the register.
7
KBF6
R
6
KBF5
R
5
KBF4
R
4
KBF3
R
3
56
KBF2
R
2
16KB+ ISP Flash & 1KB RAM embedded
KBF1
R
1
Ver.C SM59D04G2 07/2009
8-Bits Micro-controller
KBF0
R
Address: FFh
0
SM59D04G2
Reset
00h